Master Course Description

No: EE 476

Title: VLSI   I

Credits: 5

UW Course Catalog Description

Coordinator: Josephine Ammer, Assistant Professor of Electrical Engineering

Goals:

1. Develop a fairly deep understanding of how IC-based random logic and datapath blocks are designed using static and dynamic CMOS technologies.
2. Give the students extensive experience with industry-standard computer-aided design tools, including Cadence (Virtuoso, Silicon Ensemble, DRC, LVS), Avanti (Hspice) and Synopsys (Design Compiler).

Learning Objectives:

1. Enable the students to successfully complete a hand analysis of the worst-case high-to-low and low-to-high switching times of a static CMOS gate.
2. Enable the students to design an entire library of area efficient static CMOS cells using the Cadence layout editor and the Hspice circuit simulator.
3. Enable the students to design a standard cell chip of moderate complexity using Synopsys for synthesis from Verilog specifications, Cadence's Silicon Ensemble for placement and routing, Cadence's DRC and LVS for verification.
4. Enable the students to design logical functions in a wide variety of CMOS technologies.

Textbooks: Rabaey, Chandrakasan, and Nikolic, Digital Integrated Circuits, A Design Perspective

Reference Texts: Smith, HDL Chip Design; Weste and Harris, CMOS VLSI Design: a Circuits and Systems Perspective

Prerequisites by Topic:

1. Basic understanding of the operation of MOS transistors
2. Basic understanding of digital logic design

Topics:

1. Introduction to CMOS;
2. CMOS inverter design
3. Design of Static Logic Circuits
4. CMOS Switch Logic Design
5. Design of Synchronous Logic
6. Design of dynamic and domino circuits

Course Structure: There are 5 hours of lecture per week, plus extensive computer laboratory time. The first five weeks of the quarter give the students a comprehensive view of the design and analysis of static CMOS digital integrated circuits. This prepares them for the second half of the quarter that includes extensive individual design projects using static CMOS. Meanwhile, in lecture, students learn to design digital integrated circuits using a variety of other MOS technologies, ranging from pseudo n-MOS to switch logic and a variety of dynamic logic families, including domino.

Design Projects:

1. CMOS Inverter Design
2. Design of a Complex Static CMOS Cell typically containing between 12 and 15 inputs
3. Static CMOS Cell Library Design
   • inverter
   • 2- through 5-input NAND
   • 2- through 4-input NOR
   • edge-triggered D flip-flop
4. Static CMOS Design Project
   • example: elevator controller
   • example: traffic light controller for a complex interchange

Computer Resources: Students are given access to the Sun Microsystem Laboratory computers upon which reside the Cadence, Avanti, and Synopsys software program.

Laboratory: Students have free access to the Sun Microsystems Laboratory computers upon which reside the Cadence, Avanti and Synopsys software programs.

Grading: 4% Homework, 40% Projects, 28% Midterm Exams (2), and 28% Final Exam.

Outcome coverage:
(a, high) An ability to apply knowledge of mathematics, science, and engineering. All of the lectures and the majority of the exams are based on math, science, and engineering knowledge. Students must learn how to analyze the propagation delay of CMOS gates starting from basic physics principles. Mathematical formulations are commonplace throughout the course. Various methods and styles of performing digital logic at the transistor level are studied.

(b, medium) An ability to design and conduct experiments, as well as to analyze and interpret data. A significant component of designing and developing a real world application, and indeed the projects in this class, is to ensure that one's system performs to specification in the intended environment.

(c, high) An ability to design a system, component or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability. In this class, students learn how to design, lay out and characterize a complete library of static CMOS cells. The students design their system, a finite state machine of their choice, starting with Verilog, including Verilog simulation. The project is a design competition in which students use the cell library they developed in addition to using the Synopsys Design Compiler for synthesis, the Silicon Ensemble placement and routing tool from Cadence, and the DRC and LVS verification tools from Cadence, as well as Avanti's Hspice. About one-half of the grade devoted to project work (or one-half of 40%) is based on the competitiveness of their design.

(d, high) An ability to function on mulit-disciplinary teams. Although not multidisciplinary since the class is in the student's selected major, the students work as memebers of two person teams to execute each of the projects.

(e, low) An ability to identify, formulate, and solve engineering problems. For each of the design projects, the student must analyze the requirements, then design, implement, and test the design, to verify its performance and characteristics.

(f, low) An understanding of professional and ethical responsibilities.

(g, high) An ability to communicate effectively. The design projects require written reports, as well as oral presentations to the teaching assistants.

(h, low) The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental, and societal context. Lecture material routinely stresses the need to consider international markets and the need to satisfy international standards.

(i, low) A recognition of the need for, and an ability to engage in life-long learning. Lecture material continually emphasizes that today's technology is tranistory and that the student must learn the basics so that these may form a foundation upon which they will understand and build future technologies. The need to continually augment one's education is emphasized.

(j, low) A knowledge of contemporary issues. Discussions of contemporary technologies, corporate needs and responsibilities, the legal impacts of designs, and the ever-evolving engineering discipline are an integral part of the lecture material.

(k, high) An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. The students become very familiar with the operation and use of state-of-the-art industrial design automation tools from Synopsys (Design Compiler for synthesis), Cadence (Virtuoso layout editor, DRC and LVS for layout verification, Silicon Ensemble for placement and routing, Spectre for circuit simulation), and Avanti (Hspice circuit simulator) and Nassada (high-speed circuit simulator). About one-half of the grade devoted to project work (or one-half of 40%) is based on the student's ability to successfully master the use of these tools.

(l, low) Knowledge of probability and statistics, including applications appropriate to electrical engineering

(m, low) Knowledge of differential equations, linear algebra, complex variables and discrete mathematics

(n, low) Knowledge of mathematics through differential and integral calculus, basic sciences, computer science, and engineering sciences necessary to analyze and design complex electrical and electronic devices, software, and systems containing hardware and software components, as appropriate to program objectives. 

Prepared By: Josie Ammer

Last Revised: 05/09/07