Cadence software is used in both the Dept. of Electrical Engineering and the Dept. of Computer Science and Engineering for a variety of courses:
EE 473 Linear Integrated Circuits. Design of linear integrated circuits applying modern MOS and BJT integrated circuit technologies: single-stage amplifiers; current-mirror DC bias and active load circuits; stability and frequency compensation of single-stage and two-stage operational amplifiers; output stages; current and voltage reference circuits.
EE 476 Digital Integrated Circuit Design. A comprehensive view of digital integrated circuit design. Topics to be covered include the design of inverters, static logic circuits, switch logic, and synchronous logic. Students design, simulate, and layout a complete digital IC using modern computer-aided design tools.
EE 477 Custom Digital CMOS Circuit Design. Design and analysis of custom CMOS digital integrated circuits. Interface circuit design, memory design, datapath design. VLSI design methodologies, scaling properties and design tradeoffs.
E E 526 VLSI III. Ultra-high speed digital logical families based on output prediction logic; high-speed division; input and output pad design; state-of the-art latch and flip-flop design; clock distribution, including PLLs and DLLs; noise considerations in high-speed digital IC design.
EE 535 Design of Digital Integrated Circuits and Systems Design of Digital VLSI. System specifications, architectures, synthesis, simulation and layout. Covering CMOS technologies with minor emphasis on ECL, GaAS.
E E 536 Design of Analog Integrated Circuits and Systems. Design of analog VLSI: specifications, design, simulation, layout. Covering CMOS and Bi CMOS technologies.
EE 541 Automatic Layout of Integrated Circuits. This course will examine the algorithms behind the following commonly used physical design automation tools: floorplanning, partitioning, placement, routing, compaction and verification.
CSE 567 Principles of Digital Systems Design. Principles of logic design, combinational and sequential circuits, minimization techniques, structured design methods, CMOS technology, complementary and ratioed gates, delay estimation and performance analysis, arithmetic circuits, memories, clocking methodologies, synthesis and simulation tools, VLSI processor architecture.
CSE 568 Advanced VLSI Laboratory. Advanced topics on MOS technology and CAD software; students design a large chip (more than 10K transistors) to be fabricated at end of term; laboratory activities include circuit and logic design, graphic layout of a chip, extraction, checking, and simulation.
We have developed a set of tutorials that step a novice user through the process of creating and verifying a layout. The tutorials take the user through the following steps:
Alec Adams (agadams <at> ee)
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Please use this information at your own risk -- and any attempt to use this information is at your own risk. We recommend using it on a copy of your data to be sure you understand what it does and under your conditions. Keep your master intact until you are personally satisfied with the use of this information within your environment.
Cadence is a trademark of Cadence Design Systems,
Last updated: Oct. 9, 2012