---------------------------- Cadence Tutorial for EE476 ---------------------------- File Name: ~cadta/cadence/tutorial/tutorial1 * This file contains more than 1000 lines (17 pages) of plain text. * This file is frequently modified according to the class need. * For the above 2 reasons, hard copy of this file is not recommanded. Please use your favorite editor to read this file. Legend ------ Feburary 1997, updated by Meei-Ling Chiang for 9504 version 4.4 Add in bind key, graphic tool bar, and hierarchical netlising October 1996, modified by Meei-Ling Chiang Change technology file to /usr/local/cadence/uw_ee/ee476/hp08.tf Add external feedthrough in Tutorial 7. September 1995, modified by Meei-Ling Chiang Add "Tutorial 7 Over the Cell Feedthrough". July 1995, modified by Meei-Ling Chiang Modify "Tutorial 3" to cover plotting a layout. May 1995, modified by Meei-Ling Chiang Add "Tutorial 6B". Modify "Tutorial 8" to cover automatic feedthrough inserting. January 1995, modified by Meei-Ling Chiang for 9403 Addi "Tutorial ?" using different executables to start Cadence. December 1994, originally written by Meei-Ling Chiang for 9304 Table of Contents ----------------- Introduction Tutorial 1 Start Cadence Tutorial 2 Create a Design Library Tutorial 3 Layout editor Tutorial 4 Design Verification: DRC and Extraction Tutorial ? About Cadence Executables and Product Licenses Tutorial 5 Abstract View and Symbol View Tutorial 6A Schematic Design Entry Tutorial 6B Design Entry by Verilog Netlist Tutorial 7 Over the Cell Feedthrough Tutorial 8 Automatic placement and Routing Tutorial 9 Hierarchial Netlisting Introduction ------------ This tutorial use a simple example, design of a CMOS combinational adder, to introduce Cadence Design Framework II and associated softwares to new Cadence users in UWEE. Readers should have basic understanding about CMOS IC design and UNIX, be familiar with at least one text editor, and know how to start X window in HP or SUN work stations in the department. Fig 1 (as in FrameMaker file 'fig1'. If you don't know how to use FrameMaker, type "help framemaker" to see how to start it. ) depicts the schematic of a simple full adder. It consists of 5 NOR gate, 3 NAND gates, and 7 INV gates. The bottom-up design of the circuit starts with the layout of these gates using Cadence layout editor 'Virtuoso'. The gate layout is then verified by cadence design rule checker and extractor 'Diva'. Cadence schematic design entry 'Composer' is used to build the schematic of the adder then placement and routing is generated automatically by Cadence Placement and Routing tool 'Preview Cell Ensemble'. This tutorial contains detail instructions on how to get a job done but not the physical concept behind it. There is "Introduction to Cadence" in ~cadta/cadence/tutorial/introduction which contains more explanation. You are encouraged to read it before you start this tutorial or any time you feel like doing so. Tutorial 1 Start Cadence ------------------------ 1.1 Prepare to start Since cadence is installed in Sun work stations ( groucho, harpo, chico, zeppo, and gummo) and HP9000/700' ( avogadro, bohr, boltzman, compton, lorentz, planck, , rydeberg, stefan, and stirling ), if you are not in these machines please remote login to one of them using "rlogin xxxx", where xxxx is the machine name. Also, Cadence window displays only on color monitor with at least 8 planes. So, if you are in B&W terminal or colored monitor which doesn't support 8 planes, logout now and find another terminal. It's recommended to create a directory named "cadence" under your home directory to store all your cadence files. Under UNIX prompt type cd to go to your home directory, then type mkdir cadence to create this directory. In order to start cadence four start-up files, ".cdsenv", ".cdsinit", ".simrc", and ".cdsplotinit" are needed in your home directory. These files reside in /usr/local/cadence/uw_ee/ee476. If you want to know whether the files are there, cd to /usr/local/cadence/uw_ee/ee476 then type "ls -a". Remember to cd back to your cadence directory when you are done. To link the start-up files to your home directory type (use mouse to cut and paste to avoid typing errors) ln -s /usr/local/cadence/uw_ee/ee476/.*c* . Symbolic links were generated in order to save your disk space. Please use "ls -a" to make sure these four files are correctly linked. Other advantages of these symbolic links are (1) you won't accidentally modify the files; (2) if the start-up files are modified by system administrators you don't need to get new copies. If for any reason you delete the links to the start-up files, you need to regenerate the link. Also, two configurarion files are needed in your cadence directory: "cds.lib" and "display.drf". Change your working directory to cadence by typing cd cadence then copy "cds.lib" and "display.drf" from /usr/local/cadence/uw_ee/ee476 to your cadence directory using cp /usr/local/cadence/uw_ee/ee476/*s*.* . Please use "ls" to make sure you have copied them correctly. These two files provides the initial condition of your design environment. Cadence will modify these two files properly along the way and they will look differently from the original files. If you accidentally delete the files, consult your TA to recover the files. Now your preparation work has done. You can start cadence by following the instruction in next section. 1.2 Start cadence Before your start cadence, make sure you are in X Window and have your DISPLAY and xhost properly set. If you are not sure about this or you have problem starting cadence latter, please consult a consultant about X window and remote display in X window. There are several ways to start Cadence depending on which Cadence products you are going to use. The ones we are going to use in this tutorial is "layout", "layoutPlus", "asicfe", "icca", and "icde". Let's start with "layout". In X-window environment under UNIX prompt, type layout The command brings out "Command Interpreter Window" (CIW) or Log window of Cadence Design Framework II. Depending on how you set up your X Window, you might need to place CIW on the screen by clicking left mouse button. Through CIW you can manage your design process and initiate various cadence softwares. In addition to CIW, "Library Manager Windowr" appears. Library Manager Window shows reference libraries including "UWanalog", "basic", "cdsDefTechLib" and "hp08". Make sure all of these libraries show in the Library Manager Window. If not, you should quit Cadence, get a new copy of "cds.lib" from /usr/local/cadence/uw_ee/ee476 directory, then start layout again. 1.3 Quit cadence To quit cadence, from CIW pull-down menu select File -> Exit... A "Exit layout?" message window will appear to confirm your command. Click "OK" to exit. Refer to Cadence manual 'Design Framework II User Guide' for more information about Design Framework II and CIW. Cadence on-line manual can be accessed in X-window by typing "openbook&" under UNIX prompt. Are you sure you have learned what you are expected to learn in this tutorial? Check out the following key words and make sure you understand what they mean. Key Words: ".cdsenv", ".cdsinit", ".simrc", ".cdsplotinit", "cds.lib", "display.drf", Command Interpreter Window (CIW), Library Manager Window, Reference Library, Pull Down Menu, Start Cadence, Quit Cadence. Tutorial 2 Create a Design Library ---------------------------------- Design libraries are the places where you store your designs. The first step of IC design in cadence is to create a design library so you can develop your design under it. Now we are going to create a design library named "tutorial" then put the design of the combinational adder in it. First of all, cd to your "cadence" directory that you created in tutorial 1, then type "layout" to start Cadence. Now we are going to create a design library named "tutorial". (1) From pull-down menu in CIW, select File -> New -> Library... This will bring out a "New Library" form. (2) Enter "tutorial" as Name. In Technology File field, select "Attach to an existing techfile". Then click left on "OK". This will bring out a "Attach Design Library to Technology File" form. (4) Select "hp08" for "Attach to Technology Library". Then click "OK". The technology file library "hp08" defines scalable CMOS 0.8 micron, single poly, triple metal technology by HP. Then the technology file is compiled and the library is created. You can see "tutorial" appears in Library Manager Window. Click "tutorial" to see what do you have in it. Of course, there's nothing there at this monent. You can check on "hp08" too. It contains NAND2, NAND3, NOR2, and NOR3 which are standard cells that you will need in this tutorial. It also has m2_m1, m2_m3, metal1_T. ...etc which are symbolic cells defined in the technology. Click left on "NAND2", you will see "abstract", "layout", and "symbol" left to it meaning that cell "NAND2" has "abstract", "layout", and "symbol" views. Click left on other cells to see what views do they have. You may notice that when you click left to select a certain library, cell, or view, the selected item will be highlighted and filled into the "selected" field to the top of the list library, cell, or view. Once you have created a design library, you can start to put your design into it. We are going to design the combinational adder from bottom up. So the basic cells including inverter (INV), 2-input and 3-input NOR gates (NOR2 and NOR3), and 2-input and 3-input NAND gates (NAND2 and NAND3) have to be created first. To create a cell named "INV" in "tutorial" library, (1) In CIW, select File -> New Cellview ... A Create New File form pops up. (2) Selct "tutorial1" as Library Name; enter "INV" as Cell Name, "layout" as View Name; select "Virtuoso" for Tool then click "OK". Cell "INV" with "layout" view in library "tutorial" will be created and opened up for you to edit. Two more windows will be brought up. The first one is Layer Select Window (LSW). The second one is Virtuoso Editing window. LSW display the layers defined in the technology. You might notice that some layer names appear more than once in LSW. For example Metal1 appears twice: one as Metal1 dg, the other as Metal1 pn. Metal1 dg is metal1 layer with drawing purpose. Layers with drawing purpose will show in the mask layout. Metal1 pn is metal1 layer with pin purpose. Layers with pin purpose are not part of the mask layout. They indicate position of I/O pins for automatic router. The position of the cursor in layout editing window is indicated by the coordinate showed on the upper left corner of the window after X: and Y:. The unit here is "lambda" which is 0.5 micron for the technology we are using (0.8um scmos technology). Move your cursor around the editing window and see the X: Y: values change with step size 0.1. Change the step size to 1 will make your design easier. (1) From Virtuoso Editing windowi pull down menu, select Design -> Options -> Display... e "Display Options form" will come up. Comment: In addition to pull down menu, you can type "e" to bring up Display Options form. This is called "bind key". Not all the menu selections have bind keys. If the selection has bind key, it will list to the right of the menu selection. (2) In Display Options form, Change "X Snap Spacing" from to 1, change "Y Snap Spacing" to 1, then click on "OK". Now move the cursor around the editing window again, you will see the X: Y: values change with step size 1. There are raw grid and fine grid (as small dots) on the window background. If you can not clearly see the raw grids, from pull down menu select "Window" -> "Zoom out by 2 Z" In addition to pull down menu and bind key "Z", "Zoom Out" is also listed in the picture tool bar to the left of the window. Find it and try it out. Also you may use up, down, left, and right arrows to move around the design window. You will need to use "Zoom in" and "Zoom out" and those arrows many times through out your design process. So it's not a bad idea to practice them a little bit now. In next tutorial, we are going to design layout views for INV. But let's save and close the cell view and take a break now. (1) From Virtuoso Editing window, Select Design -> Save, then Window -> Close. (2) From CIW, select File -> Exit Are you sure you have learned what you are expected to learn in this tutorial? Check out the following key words and make sure you understand what they mean. Key Words: Desgin Libary, Technology File, Cell, View, Virtuoso Editing Window, Layer Select Window (LSW), Metal1 dg, Metal1 pn, (X: Y:), Display Options, Bind Key, X Snap Spacing, Y Snap Spaing, Raw Grid, Fine Grid, Zoom In, Zoom Out, Graphic Tool Bar. Tutorial 3 Layout Editor ------------------------ In this tutorial, the layout for cell "INV" is designed using cadence Layout Editor (Virtuoso). You are supposed to understand the structure and layout of PMOS and NMOS transistors very well. If not, please read relative material before you start or when you have trouble continue. Now cd to your cadence directory and start cadence with command "layout". Then You need to open INV layout view for editing (1) In Library Manager window, click left on "tutorial". You will see "tutorial" "INV" and "layout" high-lighted. (2) In Library Manager pull down menu, select File -> Open... The most common shape in a layout is rectangle. To draw rectangles (1) From LSW select a layer by clicking left on it. You will see the selected layer surrounded by wider border. (2) From Virtuoso Editing window pull down menu, click left to select Create -> Rectangle r Comment: Create Rectangle has bind key "r", and it is listed in graphic tool bar too. (3) In the layout design window click left on the first corner of the rectangle, then click left on the second corner. A rectangle is formed. (4) If this is not the rectangle you want, from menu select Edit -> Undo u to undo the action. (5) If you want to draw another rectangle on current drawing layer, simply click left on the two corners of the rectangle. (6) If you want to draw rectangles on another layer, in LSW click left on the layer to change the drawing layer then click left on the two corners. (7) If you have finished drawing rectangles, hit on the key board to exit from "Create Rectangle" command. Now we are going to build a PMOS transistor and a NMOS transistor by drawing rectangles in various layers. Notice that we are using Nwell technology and the layers below are layers with drawing purpose. Please do every rectangle with extra care. To make your drawing easier, you may use Design -> Option to change X and Y Sanp Spacing to 1. Refer to Tutorial 2 on how to do this. Layer two corners another rectangle another one ------------------------------------------------------------------------------- Active dg ( 0, 36),(12, 48) ( 0, 8),(12, 20) Pselect dg (-2, 34),(14, 50) Nselect dg (-2, 6),(14, 22) Poly1 dg ( 5, 6),( 7, 51) ( 0, 24),( 5, 28) Nwell (-5, 28),(16, 59) ------------------------------------------------------------------------------- Then we are going to connect the PMOS and NMOS to form a inverter. Notice that "ActX" is contact layer which connects Metal1 and Active. "ViaX" is via which connects Metal1 and Metal2. "P1con" is contact layer which connects Metal1 and Poly1. Layer two corners another rectangle another one ------------------------------------------------------------------------------- Metal1 dg ( 0, 36), ( 4, 52) (-2, 52), (14, 56) ( 8, 8), (12, 48) Metal1 dg ( 0, 24), ( 4, 33) ( 0, 4), ( 4, 20) (-2, 0), (14, 4) ActX dg ( 1, 1), ( 3, 3) ( 1, 9), ( 3, 11) ( 1, 13), ( 3, 15) ActX dg ( 1, 17), ( 3, 19) ( 1, 37), ( 3, 39) ( 1, 41), ( 3, 43) ActX dg ( 1, 45), ( 3, 47) ( 1, 53), ( 3, 55) ActX dg ( 9, 9), (11, 11) ( 9, 13), (11, 15) ( 9, 17), (11, 19) ActX dg ( 9, 37), (11, 39) ( 9, 41), (11, 43) ( 9, 45), (11, 47) Active dg ( 0, 0), ( 4, 4) ( 0, 52), ( 4, 56) Pselect dg (-2, -2), ( 6, 6) Nselect dg (-2, 50), ( 6, 58) Metal2 dg ( 0, 29), ( 4, 33) ( 8, 29), (12, 33) ViaX dg ( 1, 30), ( 3, 32) ( 9, 30), (11, 32) P1con dg ( 1, 25), ( 3, 27) ------------------------------------------------------------------------------- It looks like the inverter layout has been finished. But in order to let the router know how to connect this cell to others, pins are need for inputs, outputs, and power supply nodes. Pins define where the wires outside the cell can be connected to the cell. In our inverter case, we need pins for in, out, vdd and ground. To create all of these pins (1) From Virtuoso pulldown menu, select Create -> Pin ^p. This brings out a Creat Symbolic Pin form. Select "shape pin" in Mode field, then a Create Shape Pin form comes out. Comment: You might get Create Shape Pin form in the first place. Comment: Bind key for Create Pin is "^p" which means "Control-p". (2) Enter "In Out_b vdd! gnd!" as Terminal Names. Term on "Create Label". When you enter more than one terminal names, Layout Editor will create these pins sequentially. Comment: "vdd!" and "gnd!" are names reserved for power pins in order to let automatic router recognize. You need to spell it exactly like what you see here. Don't use these names for other purposes. (3) The first pin which will be created is "In". In LSW, select Metal2 pin layer. It is the Metal2 layer with pin purpose. In Create Shape Pin form, select "input" as I/O type and select "top" and "bottom" as Access Direction ( you need to unselect left and right). Then move cursor to the layout window and click left on ( 0 , 29) and ( 4, 33) to place the pin. Then click on ( 2, 31) to attach the label. You will see "in" disappear from Terminal Names field meaning that pin "in" has been placed. (5) The second pin which will be created is "Out_b". Select "output" as I/O type Then click on ( 8 , 29) and ( 12, 33) to place the pin, click on ( 10, 31) to place the pin name. You will see "out" disappear from Terminal Name filed. Comment: Metal2 pins should have top and down access direction. Metal1 pins should have left and right access direction. (6) For "vdd!", select Metal1 pn layer, select inputOutput as I/O Type, and select left and right as Access Direction (unselect top and down). Click on (-2, 52) and (14, 56) to place pin, then (6, 54) to place pin name. (7) For "gnd!", click on (-2, 0) and (14, 4) to place pin then (6, 2) to place pin name. (8) Click "Hide" to finish creating pins. You have just finished the design of an inverter layout. You need to save it by selecting Design -> Save. This is a long tutorial. You deserve a good rest. Select Window -> Close to exit layout editor, then in CIW select Open -> Quit to quit Cadence. Refer to 'Virtuoso Layout Editor User Guide' for more information about layout Editor. Key Word: Create Rectangle, Undo, Create Pin, Create Symbolic Pin form, Create Shape Pin form, Create Label, vdd!, gnd!, I/O type, Access Direction. Tutorial 4 Design Verification: DRC and Extraction -------------------------------------------------- In this tutorial you are going to verify the inverter layout designed in the previous tutorial by Design Rule Checking (DRC) and Hspice Netlist Extraction. You are supposed to have basic understanding about design rules. If not, please read relative material before you start or when you have trouble continue. Information about design rules can be found in /usr/local/cadence/uw_ee/doc/scmos-rules-rev7.ps It's a 28 page postscript file. It's recommended that you use postscript viewer (such as ghostview) to read it. Also there is a 1-page summary of the design rules in /usr/local/cadence/uw_ee/doc/rule_summary.ps You might want to print it out. Let's start working. First of all, start cadence layout tools using "layout" command. Then bring out your INV layout view for editing. Refer to the beginning of Tutorial 3 on how to bring out an existing cell view for editing. Now we are going to check if there are any DRC errors in the layout. (1) From Virtuoso menu, select Verify -> DRC... This brings out a DRC from. (2) Click "OK" on DRC form. It takes a while to check all the DRC rules defined in the technology files. You can see those rules run across CIW very fast. After DRC checking is done, DRC errors will flash on the layout window. There is one error in this case. To see what the error is (1) From Virtuoso menu select Verify -> Maker -> Explain. Then click on the flashing error. This bring out a marker text window with explanation. You can see the reason for DRC error is "Sourcedrain active must be at least 5 from well edge (Mosis rule 2.3)". (2) Place cursor in Virtuoso window, press to exit from maker explain. We have to fix the error before we go any further. Simply make the Nwell wider will do it. So (1) From Virtuoso menu, select Edit -> Stretch s (2) Place cursor on the right edge of the Nwell. You will see the right edge of the Nwell covered by yellow dashed line. (3) Click on the right edge (you will see the four edges turn yellow) then stretch the edge one unit to the right by move the cursor. Click to relocate the edge. Comment: (X: Y:) and (dX: dY:) to the top of the layout window give you idea about how much you drag. You need to do DRC again to make sure you did everything right. So do it now. You will find no error this time. Save your design before you go any further. If you need a plot of the layout, this is how you do it. (1) If you wish to put rulers in your layout to show or measure the size, from Virtuoso menu select Misc -> Ruler k. Click left on (-10, -2) then (-10, 59) to place the first ruler. Zoom out a little bit then click left on (-5, 64) then (17, 64) to place the second ruler. (2) To plot, from Virtuoso menu select Design -> Plot -> Submit... A Submit Plot Form comes out. (3) Make sure Library name, Cell Name and View Names are what you expect. Choose "select" for Plot Area, clik on (-2, -20) then (23, 70). Make sure the coordinates have been properly entered into Plot Area field. Unselect Plot With "headder" (This will save your printing quota). Click on "Plot Options". This brings out Plot Options form. (4) In Plot Options form, turn on "Center Plot". The default Plotter Name is "ps 13". If you want to plot to a different Plotter Name, choose the one you want. If you are on Sun workstation or you want to plot to a postscript file, turn on "Send Plot Only to File" and fill in "inv.ps". Comment: Plotting doesn't work well for Sun workstations. Therefore you need to plot to a postscript file first, then sent the postscript file to printers. (5) Click "OK" on Plot Options form, then click "OK" on Submit Plot form. Your cellview will be printed and a mail reporting the printing result will be sent to your account. If you don't want to receive this kind of mail, you should term "Mail Log To" off in Plot Options form. If you chose to plot to a file, "inv.ps" should locate in the directory where you start Cadence. You may print it on any printer just as you print any postscript files. You may close the INV layout view and quit Cadence now. To verify the function of this inverter, you need to extract the spice netlist from the layout then simulate it. The process may be not as straightforward as you think. First, a extracted view has to be generated from the layout view. Then spice netlist is generated from the extracted view. To generate the extracted view, (1) Start Cadence using "layoutPlus". (2) Open layout view of INV in tutorial library for editing. Refer to the beginning of Tutorial 3 on how to do this. (3) In Virtuoso window, select Verify -> Extract... A Extractor form appears. (4) Make sure Extract Method is "flat", Rule File is "divaEXT.rul" and Rule Library is "hp08" then click "OK". Cadence extractor will extract the layout and save it as extracted view. You can see the extracted view appears in Library Manager window under INV. You may close the layout view now. Let's take a close look at the extracted view first. (1) Open extracted view of INV for editing. The extracted view looks similar to the layout view. You should notice that there are no Nselect and Pselect in extracted view. Also, It contains devices extracted from layout view. You will see them in next step. (2) From Virtuoso menu, select Window -> Zoom In, then click on (5, 19) then (6, 21). You will see a "nmos4" which means 4 terminal nmos transistor which was extracted from your layout view. Comment: Always search the upper left corner of the transistor gates for the extracted transistors. (3) From Virtuoso menu, select Design -> Option -> Display... e This brings out an Editor Option window. Change Display Level from 0 to 20 then click OK. It expends the display level and gives you a nmos symbol with node names (Out_b, In and gnd!), instance name (0) and device parameters (w, l). Comment: Bind key to expand Display Level to 20 is "F". Bind key to change Display Level back to 0 is "Control-f" which means press Control and f at the same time. (4) From Virtuoso menu, select Window -> Fit All f Then use Window -> Zoom In to zoom to (5, 47) (6, 49). You will see a pmos transistor and a paracitic capacitor. Please take some time identify the node names (In, vdd!, and Out_b), instance names(1 which is the pmos and 5 which is the capacitor) and device parameters (w, l, and c). (5) Press "Control-f" to change display level back to 0. You will see a pmos4 (which is the 4-terminal pmos transistor) and a pcapcitor (which is the parasitic capacitor). nmos4, pmos4, and pcapacitor are the devices you will see in your extracted design. To generate Spice netlist from the extracted view, (1) In Virtuoso editing window, select Tools -> Simulation -> Other. This adds simulation to the menu. (2) Select Simulation -> Initialize... A Initialization Environment form appears. Click "OK". (3) Another Initialize Environment form appears. The Simulator Name in the form is "other" now. Press and hold left mouse button on "other" and change it to "hspice". Then click OK. Cadence will prepare a directory named "spice.run1" to store your simulation data. (4) Select Simulation -> Options ... This brings out Simulation Environment Options form. Turn on "Use Hierarchical Netlister" then click OK. Comment: Hierarchical Netlister gives you a more readble netlist than flat netlister. (5) Select Simulation -> Netlist/Simulate. This brings out Netlist and Simulate form. Make sure Library, Cell, and view names are what you expected, turn off "simulate", turn off "Run in Background", then click "OK". Comment: You can't perform Hspice simulation here because Cadence-Hspice interface haven't been set up yet. (5) The extracted netlist is in /cadence/spice.run1/netlist Use any text editor to open "netlist" and take a look at it. cx6 in gnd 2.262e-15 cx5 in vdd 1.599e-15 cx4 out_b gnd 3.04e-16 cx3 out_b vdd 3.04e-16 cx2 in vdd 1.9e-16 These are paracitic capacitors. "6", "5", ... are instance names. They should match the instance names in the extracted view. mx1 out_b in vdd vdd pmos4 w=6e-06 l=1e-06 ad=1.5e-11 as=1.5e-11 pd=1.1e-05 +ps=1.1e-05 mx0 out_b in gnd gnd nmos4 w=6e-06 l=1e-06 ad=1.5e-11 as=1.5e-11 pd=1.1e-05 +ps=1.1e-05 These are mos transistors. Again, "1" and "0" are instance names which should match the instance names in the extracted view. (6) To locate the devices in the netlist in the extracted view, press "F" to expand display level then in Virtuoso menu, select Edit -> Search... This brings out Search form In Search form, turn on "Zoom To Figure". Make sure "inst" is selected for "Search for" then click "Apply". Search finds you an nmos. Click on "Zoom out" a few times until you can identify its location in your layout. Click "next" in the Search form to find the next instance. Again, click "Zoom out" a few times until you know where it is. Try to match the instance in the extracted view with the device in the netlist. This is very important when you try to debug your design later. /* You can use Edit -> Search to find a specific instance in the extracted view. Just click on "Add Criteria" in the Search form. Then change "cell name" to "inst name", fill in the instance name, turn on "Zoom to Figure", and click "Appply". */ (7) If you need the transistor models, they are in /cadence/spice.run1/control Please use your favorite editor to change device model name "CMOSN" to "nmos4" and "CMOSP" to "pmos4" in order to match the device name in the hierarchical netlist. Comment: If you use flat nelister, you don't need to change them. Anyway, always check the device model names in the model cards and in the device cards to see if they matches each other. You may put together "control" and "netlist" then add in your analysis commends to form a legal hspice input file. Please refer to Hspice tutorial in ~cadta/hspice/tutorial if you need to learn how to use hspice. You can quit Cadence now. If the layout view is modified after spice netlist extraction and you want an updated spice netlist, you need to (1) perform Verification -> Extraction on layout view to obtain updated extracted view (2) then perform Simulation -> Netlist/Simulate on the updated extracted view to obtain updated spice netlist. To save your disk space, you can use "spice.run1" for Netlist/Simulation again and again. Just remember to rename "netlist" before next Netlist/Simulation otherwise the new "netlist" will replace the old one. Refer to 'Diva: Interactive Design Rule Checking' for more information about DRC and extraction. Key Words: Design Rule Checking (DRC), Ruler, Plot Area, Headder, Center Plot, Extracted View, pmos4, pcapacitor, nmos4, Instance Name, Master Name, Fit All, Initialize, "netlist", "control", Search Tutorial ? About Cadence Executables and Product Licenses -------------------------------------------------------- If you are confused about why you need to start Cadence using different commands when doing different jobs, read this tutorial. You can skip this tutorial or read it later without affecting your progress. Cadence is a very big product family. It not only contains products that perform digital and analog physical design but also have products to perform digital and analog simulation in various levels. It costs a lot of memory to bring all of this together. Therefore, it is very inefficient if you use only a few products but call the whole family to sit in the memory doing nothing. Also, we have only limited copies of license for each product. When there are too many users and the licenses for certain products run out, you can't use the product. To solve both memory and license problems, Cadence came out with different executables for different design phases. Each executable calls for only a portion of the product family and occupies only licenses of the products it calls. When you run cadence, always make sure you are using the smallest executable that fits your need. The following provides the guideline for choosing proper executables. Job Executable ------------------------------------------------------------------------------- layout only layout layout editing and drc layout layout, abstract editing, drc, and extraction layoutPlus extraction, spice netlist generation asicfe schematic entry and Verilog in icde PRflatten asicfe place and route icca -------------------------------------------------------------------------------- Tutorial 5 Abstract View and Symbol View ---------------------------------------- Now the INV cell has layout and extracted views. As an lowest level library cell, it needs two other important cell views. Abstract view: This view is necessary for automatic layout tools. It contains only cell boundary and I/O pins. Symbol view: This view is necessary for schematic design entry. It is the symbol which represents the cell. If you perform design entry by verilog netlist, you don't need to generate symbol view by yourself. To generate abstract view for INV (1) Start Cadence using "layoutPlus". (2) Open layout view of INV to edit. (3) In Virtuoso menu, select Tools -> Abstract. This brings out a Select PR Engines window. Make sure CE/BE is selected then click "OK". This adds "Abstract" to the layout menu. (4) Select Abstract -> Auto Boundary. This will generate a cell boundary box in prBoundary layer. (5) Select Abstract -> Set Cell Props... This brings out a Set Cellview Properties form. Make sure that Cell Type is "standard", Cell Class is "none", then click "OK". Comment: If there is no proper Cell Type and Cell Class for your cell, auto placement and route will fail. (6) Select Abstract Abstract -> Abgen... This brings out Abstract Generation form. Click "OK". Fill in "hp08" for Rules Library. Then click "OK". Comment: It is very important that you fill in "hp08 for Rules Library very time you perform Abgen. Or Cadence can not find the Abgen Rule file. Then an abstract view will be generated. Please open the abstract view and take a close look at it. You can close INV abstract view, save and close INV layout view, then quit cadence now. To generated symbol view for INV (1) Start Cadence using "icde". (2) In CIW menu, select File -> New -> Cellview ... A create New File form appears. Fill in "tutorial" for Library, "INV" for Cell, and "symbol" for View, and select "Composer-Symbol" for Tool, then Click "OK". This brings out a Composer-Symbol Editing window. (3) In Composer menu, select Design -> Create Cellview -> From Pin List ... This brings out a Cellview From Pin List form. (4) Type "In" as Input Pins, "Out_b" as Output Pins, "INV" as Cell Name. Change View Name to "symbol". Unselect Edit Options. Click "OK". Comment: Pin names in symbol view must be exactly the same as pin names in layout view or you will experience huge problems when doing auto placement and routing. Comment: Default power pins vdd! and gnd! should not appear in symbol view. The symbol view will be generated and brought out in symbol editing window. You may close symbol window after you exam the symbol view. There are other lowest level cells in our design: NOR2, NOR3, NAND2, and NAND3. They should have at least layout and abstract views. If you are going to do schematic entry, symbol views are necessary too. Usually you need to generate all of these views by yourself. However to save your time on tutorial, you may copy the views from "hp08" library. To copy these views (1) In Library Manager window, click left on "hp08". Make sure only "hp08" is selected and highlighted. If any cells or views are selected, move the cursor to the selected cell field, use to delete the text. (2) Press and hold middle mouse button on "hp08" and select Copy... This will bring out a Copy form. (3) The Copy form list all the cells and views in "hp08" library. A green dot in front of a listed cellview indicates the cellview is selected to be copied. Click left on the green dot to unselect "m2_m1", "m2_m3", "Metal1_T", "Metal2_T", "Metal3_T", and "Poly1_T". Fill in "tutorial" for Destination Library. Then click "OK". Then the views will be copied from "hp08" to "tutorial". Click left on "tutorial", you will see "NAND2", "NAND3", "NOR2", and "NOR3" now. You might want to check if they have "abstract", "layout", and "symbol" views. Refer to 'Preview Library Development Reference' and 'Composer Design Entry reference' for more information about abstract and symbol generation. Key Words: Abstract View, Symbol View, Cell Boundary, Cell Type. Tutorial 6A Schematic Design Entry ---------------------------------- There are two ways to enter hierarchical design into Cadence: by schematic design entry, and by netlist (usually Verilog netlist) input. If you choose to use schematic entry, continue on this tutorial. If you choose to do verilog netlist input, you may skip this tutorial and go directly to Tutorial 6B Design Entry by Verilog Netlist. We have finished developing the lowest level library cells. In this tutorial we are going to build the combinational adder from these cells by schematic entry. If you have quited Cadence from previous tutorial, start cadence using "icde" now. We need a library cell "ADDER" with "schematic" view to store the adder schematic. Please use File -> New -> Cellview to generate and open a "schematic" view for cell "ADDER" in "tutorial" library. You should select "Composer-schematic" for Tools when fill in Create New File form. The most important procedure in design entry is importing library cells as components in the design. To add inverters to your design (1) From Composer-Schematic menu, select Add -> Component ... i This brings out Add Component form. (2) Fill in "tutorial" as Library Name, "INV" as Cell Name, "symbol" as View Name and "inv1 inv2 inv3 inv4 inv5 inv6 inv7" as Instance Names. (3) Move cursor to the schematic window. You will see an instance image moving with the cursor. This is inv1. Click left on a proper spot to place it. (4) As moving the cursor in schematic window, you will see another instance image moving with the cursor. This is inv2. Click left on a proper spot to place it. (5) Move the cursor and place inv3 to inv7 on proper spots. You might need to zoom out the schematic window in order to put some more component in it. Select Window -> "Zoom Out By 2" to do it. You can zoom out and zoom in the window any time you want through out the design process. To create "nor1" to "nor4" from "NOR2", change Cell Name to "NOR2", fill in "nor1 nor2 nor3 nor4" as Instance Names, and click left to place. Mimic the same action to create "nor5" from "NOR3", "nand1" and "nand2" from "NAND2", and "nand3" from "NAND3". Finally, press to exit Create Instance. You can move any instance by pressing and holding the left mouse button on it, dragging it to the destination. Make sure you are moving the instance, not the texts in it. If you do something wrong, select Edit -> Undo to undo it. Refer to fig1 to see where to put the instances. After the instances are created and placed, you can connect them by wires to form the adder. To create a wire (1) From Composer menu, select Add -> Wire (narrow)... w (2) Click left on the starting point, click left on as many transition points as you want, then double click left to end the wire. Then we need to create pins for input and output nodes. To do this (1) From Composer menu, select Add -> Pin ... p An Add Pin form appears. (2) Type in "a b c carry sum" as Pin Names. Make sure the Direction is "input". (3) Move cursor to schematic window. Then click left to place pin "a", "b", then "c". (4) Move cursor back to Add Pin form, change Direction to "output". Then move cursor to the window, click to place "carry" and "sum". Remember to connect pins to the schematic with wires. Then the design entry is done. Save your design by selecting Design -> Check and Save. If you want to use cell 'ADDER' as components in other design, you need to generate a symbol view for it. To do this (1) From schematic menu, select Design -> Create Cellview -> From Cellview ... This brings out a Cellview From Cellview form. (2) Make sure Library Name is "tutorial", Cell Name is "ADDER", From View Name is "schematic", To View Name is "symbol". Select "Display Cellview" and unselect "Edit Options". Click "OK". A symbol view will be generated for adder according to its schematic view. Then the symbol view will be opened for you. After examing the symbol view, you may close it then save and close the schematic view. For more information about schematic design entry, refer to 'Composer Design Entry User Guide'. Key Words: Schematic View, Component, Wire, Pin Tutorial 6B Design Entry by Verilog Netlist ------------------------------------------- This tutorial shows you how to perform Design Entry by Verilog Netlist in Cadence. A structural Verilog file describing the combinational adder is in ~cadta/cadence/verilog/adder.v It it recommanded that you spend time reading the file to see what a legal verilog structural file for Cadence Verilog Input looks like. There are comment lines in the file which describe the necessary parts to form a legal Verilog structural file. If you are not familiar with Verilog Netlist, please refer to Cadence on-line manual 'Verilog-XL Tutorial' and 'Verilog-XL Reference' for detail. To input the Verilog file into Cadence, start Cadence with "icde". Then (1) From CIW, select File -> Import -> Verilog ... This brings out a Verilog In form. (2) Fill in "tutorial" as Target Library Names, "/users/u5/cadta/cadence/verilog/adder.v" as Verilog Files To Import. Click OK. It takes a while to complete the import process. You can monitor the progress in CIW. It generates schematic views for INV, NAND2, NAND3, NOR2, and NOR3. If you didn't generate symbol views for INV, NAND2, NAND3, NOR2, and NOR3, it generates them too. It also generates schematic and symbol views for adder according to the verilog netlist. If you don't see "adder" appearing in Library Manager window, don't panic. Check the CIW window, if it tells you "Generated sheet 1 for schematic adder" then you are fine. Just Close Library Manager window by File -> Exit, then restart Library Manager by (From CIW menu) Tools -> Linrary Manager ... You should be able to see "adder" now. You may quit Cadence now. Tutorial 7 Feedthrough ---------------------- This tutorial tells you how to design an "explicit feedthrough" cell and how to add "implicit feedthrough" to a cell. If you are not interested in this you may skip this tutorial. A. Implicit Feedthrough Start Cadence with "layoutPlus" then open "layout" view of NAND3 in "tutorial" library for editing. Between "In0" pin and "In1" pin, there is an area bounded by (26, 56) and (30, 0) where Metal2 can run through the cell from top to bottom without violating the design rules. Implicit feedthru is a Metal2 jumper pin with up and down access direction which tells the router that a Metal2 signal path can run through the cell. To generate implicit feedthru for NAND3 (1) In LSW select Metal2 pn. In virtuoso menu select Create -> Pin ... ^p A Create Symbolic Pin Form appears. Click on "shape pin" to change it to Create Shape Pin form. (2) Fill in "InOut" as Terminal Names, turn on Create Label, select "jumper" for I/O Type, select, select "top" and "bottom" for Access Direction (make sure left and right are unselected). (3) Click left mouse button on (26, 32) then (30, 28) to place the pin, then on (28, 30) again to attach the pin name. (4) Press to end Create Pin. Use Design -> Save to save the change. When ever a layout view is modified, the abstract view of the cell has to be regenerated. (1) In Virtuoso menu, select Tools -> Abstract. This adds Abstract to the menu. (2) Select Abstract -> Abgen. A Create Abstract form appears. Change Rule Library to "hp08", Click OK. This will regenerate the abstract view. There is already an implicit feedthru in NOR3. You may take a look at it. B. External Feedthrough To make an external feedthrough master cell call "feedthru", first we generate it's layout view, then generate it's abstract view. (1) Use File -> New -> Cellview to generate "layout" view of cell "feedthru" in library "tutorial". (3) Use Create -> Rectangle to draw the following metal wires, contacts and boundary. ---------------------------------------------------- Layer two corners another rectangle ---------------------------------------------------- Metal1 dg ( 0, 6),(12, 2) ( 0, 58),(12, 54) Nselect dg ( 2, 52),(10, 60) Pselect dg ( 2, 0),(10, 8) Active dg ( 4, 54),( 8, 58) ( 4, 2),( 8, 6) ActX dg ( 5, 55),( 7, 57) ( 5, 3),( 7, 5) Nwell dg ( 0, 30),(12, 61) ---------------------------------------------------- Comment: Every standard cell inclusing feedthrough cell should have at least one well contact which connects well to vdd! and one substrate contact which connects substrate to gnd! (4) Use Create -> Pin to define the following pins Remember to change to Shape Pin form if it is not it in the fist place. ------------------------------------------------------------------------ Layer terminal name I/O Type two corners Assess Direction ------------------------------------------------------------------------ Metal1 pn gnd! Jumper (0, 6),(12, 2) left, right Metal1 pn vdd! Jumper ( 0, 58),(12, 54) left, right Metal2 pn InOut Jumper ( 4, 32),( 8, 28) top, bottom ------------------------------------------------------------------------ (5) Select Tools -> Abstract. Select CE/BE for P&R Engine. (6) Use Abstract -> Auto Boundary to generate cell boundary. (7) Select Abstract -> Set Cell Props ... Make sure Cell Type is "standard", select "feedthru" as Cell Class, then Click OK. (8) Use Abstract -> Abgen ... to generate abstract view. Remember to fill in "hp08" as Rules Library. (9) Save then close the layout view. You may quit Cadence now. Key Words: Implicit Feedthrough, Explicit Feedthrough, Jumper Pin Tutoria 8 Automatic Placement and Routing ------------------------------------------ Now you are ready for automatic placement and routing your "adder". But cadence requires one more procedure before placement and routing, called PR Flatten. PR Flatten should be performed on your highest level cell. It flattens your hierarchical design to the level you desire. In our adder case we flatten it to the lowest level standard cells. To perform PR Flatten, start Cadence using "icca". Then (1) From CIW menu, select File -> Export -> PR Flatten. A PRflatten form appears. Remember you should perform PR Flatten only on your toppest level cell. (2) Type in "tutorial" as Library Name, "adder" as Cell Name and "schematic" as View Name. Make sure Run is "Generate Physical Hierarchy". Click "OK". This will generate "autoLayout" view for adder. Then we can automatically place and route "adder". (1) Open "autoLayout" view of adder for editing. Comment: All the cells should be stacked with order inside the defualt layout area. If you see overlapping, there might be something wrong with your standard cells. The most common error is that you didn't set Cell Type as "standard" for standard cells. (2) In Virtuoso menu, select Tools -> Floorplan/P&R -> Cell Ensemble. This will change the Virtuoso menu from layout to Cell Ensemble menu. Also an Object Selected Winodw (OSW) pops up. (3) Select Floorplan -> Reinitialize. A Initialize Floorplan form appears. Change Chip Aspect Ratio from "1" to "0.5". Click "OK". Initialization estimates layout area, puts I/O pins to the top of the default layout area, and puts standard cells to the right of the default layout area. Comment: Usually, the Chip Apsect Ratio should be 1. We choose 0.5 here just to demonstrate the function of feedthrough. (4) Select Floorplan -> I/O place. This brings out IO Placer form. Click "OK". (5) Select Place -> Sequencer. A Placement Sequencer form appears. Make sure only "Justify IO" and "Place Standard Cells" are selected. (6) Click on "place" button. This brings out a "initial place" form. If you have designed feedthru master cell "feedthru" and wish to use it, turn on "Insert Feedthru". Fill in "tutorial" as FeedThru Library Name, "feedthru" as Feedthru Master Name, and make sure Feedthru Master view is "abstract". Change Placement Snap Grid to 1. Click "OK". (7) Click "OK" on Initial Place form. This will automatically insert feedthrough and place all the cells. You will see one feedthru cell being placed in the design. (8) Select Route -> Sequencer. A Route Sequencer form appears. Make sure only "Global Route Optimize" and "Save Design" are unselected. Click on "detail" to bring out Detail Route Form. (9) In Detail Route Form, select "3 Layers" for Routing Layers, change Routing Snap Grid to "1" , click OK. Comment: You may select "to instance blockage" for channel boundary extending to save routing area next time. But not this time, becuase I wish you to obtain an easy-to-read layout for fast learning. (10) Click "OK" button in Route Sequencer Form. This will initiate routing process. It takes a while to finish the routing process. You may monitor the routing process from CIW. When the process is done, the it brings up the routed autoLayout view. The last step is to generate layout view from autoLayout view. (1) Select Floorplan -> Replace View. This will bring out a Replace View form. (2) In the form, select "all" for Instance To Work On. Make sure To View Name is "layout". Click "OK". This will replace all the standard cells' abstract view by layout view. (3) Select Tools -> Compactor. This will change the menu to compactor menu. (4) Select Compact -> Convert to Geometric. A Convert to Geometric form appear. Click "OK". This will generate layout view for adder according to the autoLayout view. Also the layout view is opened for editing. (5) In layout window, select Design -> Option -> Display. This will bring out a Display Options form. In Display Levels fields, fill in "0" for From and "20" for To. Click "OK". This will expend the autoLayout view down 20 levels. Comment: Bind Key to expand display level to 20 is "F". Now you can see the final layout. If you take a close look at it, you might find that neither implicit feedthru nor the explicit feedthru are not used by the router. It is very common in a small design like this. You will see the router use feedthru more often when your desgin grows to more than 100 cells. You need to do DRC on this layout too, becuase sometimes router makes mistakes. (1) In adder layout window, select Tools -> Layout to change the menu back to layout menu. (2) Select Verify -> DRC. This brings out DRC form. Make sure that Rule Library is hp08 and Rule file is divaDRC.rul. Click "OK". You shouldn't have any errors this time. But if you have errors now or in the future and you wish to fix it, this is what you can do. (1) Locate the error and get explanation on it by Verify -> Markers -> Explain. (2) Select the instance that contains the error by click on it. The instance might be a standard cell or a routing channel. You will see it high lighted when being selected. (3) Select Design -> Hierarchy -> Descend. This bring out the layout view of the selected instance. (4) Fix the error and save the change. (5) Design -> Hierarchy -> Return to return to the original view. (6) Redo DRC. You may quit Cadence now. For more information about floorplan and P&R refer to 'Preview Floorplan User Guide' and 'Preview Cell Ensemble Reference'. Tutorial 9 Hierarchical Netlisting ---------------------------------- In this tutorial, a hierarchical hspice netlist will be generated from adder layout view. In order to obtain hierarchical netlist, first a hierarchial extracted view has to be generated from layout view. (1) Start Cadence with "layoutPlus", then open adder layout view for editing. (2) In adder layout menu, select Verify -> Extract. This brings up Extractor form. (3) Select "incrememtal hier" fro Extract Method. Make usre Rules File is "divaEXT.rul", Rule Library is "hp08". Click OK. This will generate extracted and excell views for adder and all the standard cells contained in adder. You may monitor the process through CIW. When the process is done, close adder layout view. Comment: It's very important that you select "incremental hier" but not "flat" if you want a hierarchical extracted view and hierarchical netlist. Comment: Hierarchical netlist is more readable but not as accurate as flat netlist. So it is recommanded that in debugging phase, select "incremental hier" here, but in final verification phase, select "flat" here. (4) Open adder extracted view for editing. (5) In adder extracted view menu, select Tools -> Simulation -> Other. This adds simulation to the menu. (6) In adder extracted menu, select Simulation -> Initialize. This brings out Initialize Environment form. Change simulation directory to "spice.run1". Click OK. (7) In adder extracted menu, select Simulation -> Options. This brings out Simulation Enviornment Options form. Turn on "Use Hierarchical Netlister". Then click OK. (8) In adder extracted menu, select Simulation -> Netlist/Simulate ... This brings up Netlist and Simulate form. Turn off "simulation" and "Run in Background". Make sure Cell Name and View Name are what you expected then click OK. The hierarchical netlister starts to nelist your design. When the process is done, Netlist and Simulation form disappears. (9) The extracted nelist is in "/cadence/spice.run1/netlist". Use your favorite text editor to read it. This is a long file compare to the previous netlist we got from INV. But it is definitly shorter than the netlist you will obtain from your final prooject design. So please spent decent amount of time now to get used to the netlist format.