S. Hauck, "Asynchronous Design Methodologies: An Overview" (PDF), Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995. Also appearing as University of Washington, Dept. of C.S.&E. TR #93-05-07, 1993.
G. Borriello, C. Ebeling, S. Hauck, S. Burns, "The Triptych FPGA Architecture" (PDF), IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 491-501, December, 1995.
C. Ebeling, L. McMurchie, S. Hauck, S. Burns, "Placement and Routing Tools for the Triptych FPGA" (PDF), IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 473-482, December, 1995.
S. Hauck, G. Borriello, "An Evaluation of Bipartitioning Techniques" (PDF), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 8, pp. 849-866, August 1997.
S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems" (PDF), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 9, pp. 956-964, September, 1997.
S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998.
S. Hauck, G. Borriello, C. Ebeling "Mesh Routing Topologies for Multi-FPGA Systems" (PDF), IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 400-408, September, 1998.
S. Hauck, Z. Li, E. J. Schwabe, "Configuration Compression for the Xilinx XC6200 FPGA" (PDF), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 8, pp. 1107-1113, August, 1999.
M. Enos, S. Hauck, M. Sarrafzadeh, "Evaluation and Optimization of Replication Algorithms for Logic Bipartitioning" (PDF), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 9, pp. 1237-1248, September, 1999.
S. Hauck, M. M. Hosler, T. W. Fry, "High-Performance Carry Chains for FPGAs" (PDF), IEEE Transactions on VLSI Systems, Vol. 8, No. 2, pp. 138-147, April, 2000.
S. Hauck, "FPGA Tools Need Hardware Assistance" (HTML), EE Times, February 16th, 2001.
K. Compton, Z. Li, J. Cooley, S. Knol, S. Hauck, "Configuration Relocation and Defragmentation for Run-time Reconfigurable Computing" (PDF), IEEE Transactions on VLSI Systems, Vol. 10, No. 3, pp. 209-220, June 2002.
K. Compton, S. Hauck, "Reconfigurable Computing: A Survey of Systems and Software" (PDF), ACM Computing Surveys, Vol. 34, No. 2. pp. 171-210. June 2002.
K. Compton, S. Hauck, "Research Focuses on Application-Specific Reconfigurable Blocks" (PDF), EE Times, September 11th, 2002.
S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, "The Chimaera Reconfigurable Functional Unit" (PDF), IEEE Transactions on VLSI Systems. Vol. 12, No. 2, pp. 206-217, February 2004.
M. L. Chang, S. Hauck, "Precis: A User-Centric Word-Length Optimization Tool", IEEE Design & Test of Computers, Vol. 22 No. 4, pp. 349-361, July-August 2005.
T. Fry, S. Hauck, "SPIHT Image Compression on FPGAs", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 15, No. 9, pp. 1138-1147, September 2005.
K. Eguro, S. Hauck, "Resource Allocation for Coarse Grain FPGA Development", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 10, pp. 1572-1581, October 2005.
A. Sharma, C. Ebeling, S. Hauck, "PipeRoute: A Pipelining-Aware Router for Reconfigurable Architectures", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 3, pp. 518-532, March 2006.
M. Holland, S. Hauck, "Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp. 291-295, February 2007.
K. Compton, S. Hauck, "Automatic Design of Area-Efficient Configurable ASIC Cores", IEEE Transactions on Computers, Vol. 56, No. 5, pp. 662-672, May 2007.
M. J. Beauchamp, S. Hauck, K. D. Underwood, K. S. Hemmert, "Architectural Modifications to Enhance the Floating-Point Performance of FPGAs", IEEE Transactions on VLSI Systems, Vol. 16, No. 2, pp. 177-187, February 2008.
K. Compton, S. Hauck, "Automatic Design of Reconfigurable Domain-Specific Flexible Cores", IEEE Transactions on Computers, Vol 16, No. 5, pp. 493-503, May 2008.
Z. Li, K. Compton, S. Hauck, "Configuration Cache Management Techniques for Reconfigurable Computing", submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
S. Phillips, A. Sharma, S. Hauck, "Layout Generation for Domain-Specific FPGAs", submitted to IEEE Transactions on VLSI Systems.
K. Compton, S. Hauck, "Automatic Design of Reconfigurable Domain-Specific Flexible Cores", submitted to IEEE Transactions on VLSI Systems.
K. Eguro, S. Hauck, "Enhancing Routing Heuristics on Pipelined-FPGAs", submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
M. Haselman, S. Hauck, "The Future of Integrated Circuits: A Survey of Nano-electronics", submitted to Proceedings of the IEEE.
J. A. Brzozowski, S. Hauck, C.-J. H. Seger, "Chapter 15: Design of Asynchronous Circuits", in J. A. Brzozowski, C.-J. H. Seger, Asynchronous Networks, Springer-Verlag, 1995.
S. Hauck, Multi-FPGA Systems, Ph.D. Thesis, University of Washington, Dept. of C.S.&E., September, 1995.
A. C. Miguel, R. E. Ladner, E. A. Riskin, S. Hauck, D. K. Barney, A. R. Askew, A. Chang, "Predictive Coding of Hyperspectral Images", in G. Motta, F. Rizzo, J. A. Storer (editors), Hyperspectral Data Compression, Springer Science & Business Media, Inc: NY, pp. 197-232, 2006.
S. Hauck, "Field-Programmable Gate Arrays", McGraw-Hill Encyclopedia of Science & Technology, 10th edition, 2006.
S. Hauck, "Field-Programmable Gate Arrays", McGraw-Hill Yearbook of Science & Technology, 2007, pp. 81-84.
M. Haselman, S. Hauck, T. Lewellen, R. Miyaoka, "Data Acquisition System for a Positron Emission Tomography Scanner", U.S. Provisional Patent Application No. 60/985,083, November 2, 2007.
S. Hauck, A. DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-based Computation, Morgan Kaufmann/Elsevier, 2008.
G. O. Stone, A Comparison of ASIC Implementation Alternatives, M.S. Thesis, Northwestern University, Dept. of ECE, October, 1996.
M. Hosler, High Performance Carry Chains for FPGAs (PDF), M.S. Thesis, Northwestern University, Dept. of ECE, October, 1997.
G. Gu, Accelerating Photoshop Applications with Reconfigurable Hardware, M.S. Thesis, Northwestern University, Dept. of ECE, May, 1999.
M. Chang, Adaptive Computing in NASA Multi-Spectral Image Processing, M.S. Thesis, Northwestern University, Dept. of ECE, December, 1999.
K. Compton, Programming Architectures for Run-Time Reconfigurable Systems, M.S. Thesis, Northwestern University, Dept. of ECE, December, 1999.
T. Fry, Hyperspectral Image Compression on Reconfigurable Platforms, M.S. Thesis, University of Washington, Dept. of EE, June, 2001.
M. Richmond, A Lemple-Ziv based Configuration Management Architecture for Reconfigurable Computing, Master's Thesis, University of Washington, Dept. of EE, July, 2001.
C. Mulpuri, Runtime and Quality Tradeoffs in FPGA Placement and Routing, M.S. Thesis, Northwestern University, Dept. of ECE, July, 2001.
S. Phillips, Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip, M.S. Thesis, Northwestern University, Dept. of ECE, July, 2001.
A. Sharma, Development of a Place and Route Tool for the RaPiD Architecture, M.S. Thesis, University of Washington, Dept. of EE, 2001.
M. Holland, Harnessing FPGAs for Computer Architecture Education, M.S. Thesis, University of Washington, Dept. of EE, 2002.
Z. Li, Configuration Management Techniques for Reconfigurable Computing, Ph.D. Thesis, Northwestern University, Dept. of ECE, 2002.
K. Eguro, RaPiD-AES: Developing an Encryption-Specific FPGA Architecture, M.S. Thesis, University of Washington, Dept. of EE, 2002.
T. Owen, Unequal Loss Protection of Hyperspectral Compressed Images on Reconfigurable Platforms, M.S. Thesis, University of Washington, Dept. of EE, 2003.
K. Compton, Architecture Generation of Customized Reconfigurable Hardware, Ph.D. Thesis, Northwestern University, Dept. of ECE, 2003.
M. Chang, Variable Precision Analysis for FPGA Synthesis, Ph.D. Thesis, University of Washington, Dept. of EE, 2004.
S. Phillips, Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip, Ph.D. Thesis, University of Washington, Dept. of EE, 2004.
M. Haselman, A Comparison of Floating Point and Logarithmic Number Systems on FPGAs, M.S. Thesis, University of Washington, Dept. of EE, 2005.
A. Sharma, Place and Route Techniques for FPGA Architecture Advancement, Ph.D. Thesis, University of Washington, Dept. of EE, 2005.
M. Holland, Automatic Creation of Product-Term-Based Reconfigurable Architectures for System-on-a-Chip, Ph.D. Thesis, University of Washington, Dept. of EE, 2005.
M. Beauchamp, Architectural Modifications to Enhance the Floating-Point Performance of FPGAs, M.S. Thesis, University of Washington, Dept. of EE, 2006.
P. Grossman, Benchmarking the Independence Architecture Adaptive Placer on the Triptych FPGA Architecture, M.S. Thesis, University of Washington, Dept. of EE, 2006.
D. DeWitt, An FPGA Implementation of Statistical Based Positioning for Positron Emission Tomography, M.S. Thesis, University of Washington, Dept. of EE, 2008.
B. Weintraub, Building BLAST for Coprocessor Accelerators Using Macah, Honors Project, University of Washington, Dept. of CSE, Spring 2008.
S. Hauck, G. Borriello, C. Ebeling, "Mesh Routing Topologies for Multi-FPGA Systems" (PDF), International Conference on Computer Design, pp. 170-177, 1994.
S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems" (PDF), ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, February, 1995.
S. Hauck, G. Borriello, "An Evaluation of Bipartitioning Techniques" (PDF), Chapel Hill Conference on Advanced Research in VLSI, pp. 383-402, March, 1995.
S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, "The Chimaera Reconfigurable Functional Unit" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.
M. Enos, S. Hauck, M. Sarrafzadeh, "Replication for Logic Bipartitioning" (PDF), International Conference on Computer-Aided Design, pp. 342-349, 1997.
S. Hauck, "Configuration Prefetch for Single Context Reconfigurable Coprocessors" (PDF), ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 65-74, 1998.
S. Hauck, M. M. Hosler, T. W. Fry, "High-Performance Carry Chains for FPGAs" (PDF), ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 223-233, 1998.
S. Hauck, Z. Li, E. J. Schwabe, "Configuration Compression for the Xilinx XC6200 FPGA" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, pp. 138-146, 1998.
S. Hauck, S. Knol, "Data Security for Web-based CAD" (PDF), Design Automation Conference, pp. 788-793, 1998.
S. Hauck, "The Future of Reconfigurable Systems" (PDF), Keynote Address, 5th Canadian Conference on Field Programmable Devices, Montreal, June 1998.
Z. Li, S. Hauck, "Don't Care Discovery for FPGA Configuration Compression" (PDF), ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , pp. 91-98, 1999.
M. L. Chang, S. Hauck, "Adaptive Computing in NASA Multi-Spectral Image Processing" (PDF), Military and Aerospace Applications of Programmable Devices and Technologies International Conference, 1999.
Z. A. Ye, A. Moshovos, S. Hauck, P. Banerjee, "CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit", International Symposium on Computer Architecture, pp. 225-235, 2000.
Z. Li, K. Compton, S. Hauck, "Configuration Cache Management Techniques for FPGAs" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, pp. 22-36, 2000.
P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Haldar, P. Joisha, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, D. Zaretsky, "A MATLAB Compiler for Distributed, Hetergeneous, Reconfigurable Computing Systems", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 39-48, 2000.
C. Mulpuri, S. Hauck, "Runtime and Quality Tradeoffs in FPGA Placement and Routing" (PDF), ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 29-36, 2001.
Z. Li, S. Hauck, "Configuration Compression for Virtex FPGAs" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, 2001.
K. Compton, S. Hauck, "Totem: Custom Reconfigurable Array Generation" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, 2001.
A. Lenharth, R. Ladner, S. Hauck, E. Riskin, A. Miguel, "Wavelet Compression of MODIS Satellite Images", Earth Science Technology Conference, August, 2001.
T. Wu, A. C. Miguel, E. A. Riskin, A. E. Mohr, R. E. Ladner, S. Hauck, "Protecting regions of interest in medical images in a lossy packet network," in Medical Imaging 2002: PACS and Integrated Medical Information Systems: Design and Evaluation, Eliot L. Siegel, H. K. Huang, Editors, Proceedings of SPIE, Vol. 4685, 137-148 (2002).
Z. Li, S. Hauck, "Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 187-195, 2002.
S. Phillips, S. Hauck, "Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 165-173, 2002.
T. W. Fry, S. Hauck, "Hyperspectral Image Compression on Reconfigurable Platforms", IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 251-260, 2002.
M. L. Chang, S. Hauck, "Precis: A Design-Time Precision Analysis Tool", IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 229-238, 2002.
T. W. Fry, S. Hauck, "Hyperspectral Image Compression on Reconfigurable Platforms", Earth Science Technology Conference, June, 2002.
M. L. Chang, S. Hauck, "Precis: A Design-Time Precision Analysis Tool", Earth Science Technology Conference, June, 2002.
K. Compton, A. Sharma, S. Phillips, S. Hauck, "Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems", International Conference on Field Programmable Logic and Applications, pp. 59-68, 2002.
A. Sharma, C. Ebeling, S. Hauck, "PipeRoute: A Pipelining-Aware Router for FPGAs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 68-77, 2003.
K. Eguro, S. Hauck, "Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development", IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 111-120, 2003.
A. C. Miguel, A. Chang, R. E. Ladner, S. Hauck, E. A. Riskin, "On-Board Satellite Implementation of Wavelet-Based Predictive Coding of Hyperspectral Images", Earth Science Technology Conference, 2003.
M. Chang, S. Hauck, "Variable Precision Analysis for FPGA Synthesis", Earth Science Technology Conference, 2003.
K. Compton, S. Hauck, "Track Placement: Orchestrating Routing Structures to Maximize Routability", International Conference on Field Programmable Logic and Applications, 2003.
K. Compton, S. Hauck, "Flexibility Measurement of Domain-Specific Reconfigurable Hardware", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 155-161, 2004.
A. Sharma, K. Compton, C. Ebeling, S. Hauck, "Exploration of Pipelined FPGA Interconnect Structures", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 13-22, 2004.
A. C. Miguel, A. R. Askew, A. Chang, S. Hauck, R. E. Ladner, E. A. Riskin, "Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation", pp. 469-479, Data Compression Conference, 2004.
M, Chang, S. Hauck, "Automated Least-Significant Bit Datapath Optimization for FPGAs", IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 59-67, 2004.
M. Holland, S. Hauck, "Automatic Creation of Reconfigurable PALs/PLAs for SoC", International Symposium on Field-Programmable Logic and Applications, pp. 536-545, 2004.
S. Phillips, A. Sharma, S. Hauck, "Automating the Layout of Reconfigurable Subsytems Via Template Reduction", International Symposium on Field-Programmable Logic and Applications, pp. 857-861, 2004.
K. Eguro, S. Hauck, A. Sharma, "Architecture-Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement", Design Automation Conference, pp. 439-444, 2005.
S. Phillips, S. Hauck, "Automating the Layout of Reconfigurable Subsystems Using Circuit Generators", IEEE Symposium on Field-Programmable Custom Computing Machines, 2005.
M. Haselman, M. Beauchamp, A. Wood, S. Hauck, K. Underwood, K. Scott Hemmert, "A Comparison of Floating Point and Logarithmic Number Systems for FPGAs", IEEE Symposium on Field-Programmable Custom Computing Machines, 2005.
M. Holland, S. Hauck, "Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC", International Symposium on Field-Programmable Logic and Applications, pp. 95-100, 2005.
A. Sharma, C. Ebeling, S. Hauck, "Architecture-Adaptive Routability-Driven Placement for FPGAs", International Symposium on Field-Programmable Logic and Applications, pp. 427-432, 2005.
A. Sharma, S. Hauck, "Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques", IEEE International Conference on Field Programmable Technology, pp. 225-232, 2005.
K. Eguro, S. Hauck, "Armada: Timing-Driven Pipeline-Aware Routing for FPGAs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 169-178, 2006.
M. J. Beauchamp, S. Hauck, K. D. Underwood, K. S. Hemmert, "Embedded Floatint Point Units in FPGAs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 12-20, 2006.
M. Holland, S. Hauck, "Improving Performance and Robustness of Domain-Specific CPLDs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 50-59, 2006.
M. J. Beauchamp, S. Hauck, K. Underwood, K. S. Hemmert, "Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs", International Conference on Field Programmable Logic and Applications, pp. 515-520, 2006.
Allan Carroll, Stephen Friedman, Brian Van Essen, Aaron Wood, Benjamin Ylvisaker, Carl Ebeling,Scott Hauck, "Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency", Department of Energy NA-22 University Information Technical Interchange Review Meeting, 2007.
Ken Eguro, Scott Hauck, "Simultaneous Retiming and Placement for Pipelined Netlists", to appear in IEEE Symposium on Field-Programmable Custom Computing Machines, 2008.
Ken Eguro, Scott Hauck, "Enhancing Timing-Driven FPGA Placement for Pipelined Netlists", to appear in Design Automation Conference, 2008.
E. A. Walkup, S. Hauck, G. Borriello, and C. Ebeling, "Routing-directed Placement for the Triptych FPGA" (PDF), ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1992.
S. Hauck, G. Borriello, S. Burns and C. Ebeling, "Montage: An FPGA for Synchronous and Asynchronous Circuits" (PDF), 2nd International Workshop on Field-Programmable Logic and Applications, Vienna, August 1992. Also appearing in H. Grunbacher, R. W. Hartenstein, Eds., Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Berlin: Springer-Verlag, pp. 44-51, 1993.
S. Hauck, G. Borriello, C. Ebeling, "Mesh Routing Topologies for FPGA Arrays" (PDF), ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1994.
S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems (Extended Abstract)" (PDF), IEEE Workshop on FPGAs for Custom Computing Machines, pp. 11-13, April, 1994.
S. Hauck, W. D. Wilson, "Abstract: Runlength Compression Techniques for FPGA Configurations" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, 1999.
K. Compton, J. Cooley, S. Knol, S. Hauck, "Abstract: Configuration Relocation and Defragmentation for FPGAs" (PDF), IEEE Symposium on FPGAs for Custom Computing Machines, pp. 279-280, 2000.
M. Holland, J. Harris, S. Hauck, "Harnessing FPGAs for Computer Architecture Education", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pg. 250, 2002.
S. Hauck, "APHYDS: Academic Physical Design Skeleton", IEEE International Conference on Microelectronic Systems Education, 2003.
M. Holland, J. Harris, S. Hauck, "Harnessing FPGAs for Computer Architecture Education", IEEE International Conference on Microelectronic Systems Education, 2003.
M, Chang, S. Hauck, "Least-Significant-Bit Optimization Techniques for FPGAs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 2004.
S. Phillips, A. Sharma, S. Hauck, "Automating the Layout of Reconfigurable Subsytems Via Template Reduction", IEEE Symposium on Field-Programmable Custom Computing Machines, pp.340-341, 2004.
A. Sharma, C. Ebeling, S. Hauck, "Architecture Adaptive Routability-Driven Placement for FPGAs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 2005.
M. Holland, S. Hauck, ""Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC", IEEE Symposium on Field-Programmable Custom Computing Machines, 2005.
S. Hauck, "Active Learning Techniques in a CAD Course", IEEE International Conference on Microelectronic Systems Education, pp. 125-126, 2007.
M. D. Haselman, S. Hauck, T.K. Lewellen, R.S. Miyaoka, "Simulation of Algorithms for Pulse Timing in FPGAs", IEEE Nuclear Science Symposium and Medical Imaging Conference, 2007.
M. Haselman, R. Miyaoka, T. K. Lewellen, S. Hauck, "FPGA-Based Data Acquisition System for a Positron Emission Tomography (PET) Scanner", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 2008.
T.K. Lewellen, R.S. Miyaoka, L.R. MacDonald, M. Haselman, S. Hauck, "Design of a Second Generation Firewire Based Data Acquisition System for Small Animal PET Scanners", to appear in IEEE Nuclear Science Symposium and Medical Imaging Conference, 2008.
Don DeWitt, Robert S. Miyaoka, Xiaoli Li, Cate Lockhart, Tom Lewellen, Scott Hauck, "Design of an FPGA based Algorithm for Real-Time Solutions of Statistics-Based Positioning", to appear in IEEE Nuclear Science Symposium and Medical Imaging Conference, 2008.
S. Hauck, G. Borriello, C. Ebeling, "Springbok: A Rapid-Prototyping System for Board-Level Designs" (PDF), 1995.
S. Hauck, A. Agarwal, "Software Technologies for Reconfigurable Systems" (PDF), 1996.
K. Compton, S. Hauck, "Mapping Methods for the Chimaera Reconfigurable Functional Unit" (PDF), Northwestern University, Dept. of ECE Technical Report, 1997.
S. Hauck, S. Knol, "Data Security for Web-based CAD" (PDF), Northwestern University, Dept. of ECE Technical Report, 1998.
S. Hauck, W. D. Wilson, "Runlength Compression Techniques for FPGA Configurations" (PDF), Northwestern University, Dept. of ECE Technical Report, 1998.
Z. A. Ye, A. Moshovos, S. Hauck, N. Shenoy, P. Banerjee, "CHIMAERA: Integrating a Reconfigurable Functional Unit into a High-Performance, Dynamically-Scheduled Superscalar Processor" (PDF), Technical Report, 1999.
Z. A. Ye, N. Shenoy, S. Hauck, A. Moshovos, P. Banerjee, "A C Compiler for a Processor with a Reconfigurable Functional Unit" (PDF), 1999.
P. Banerjee, A. Choudhary, S. Hauck, N. Shenoy, C. Bachmann, M. Chang, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, "MATCH: A MATLAB Compiler for Adaptive Computing Systems", 1999.
K. Eguro, S. Hauck, "synFPGA: Application Specific FPGA Synthesis", Northwestern University, Dept. of ECE, Technical Report, 2000.
K. Compton, J. Cooley, S. Knol, S. Hauck, "Configuration Relocation and Defragmentation fo FPGAs", Northwestern University, Dept. of ECE, Technical Report, 2000.
S. Hauck, Z. Li, "Improved Configuration Prefetch for Single Context Reconfigurable Coprocessors" (PDF), Technical Report, 2000.
T. Owen, S. Hauck, "Arithmetic Compression on SPIHT Encoded Images", University of Washington, Dept. of EE Technical Report UWEETR-2002-0007, 2002.
M. Holland, J. Harris, S. Hauck, "Harnessing FPGAs for Computer Architecture Education", University of Washington, Dept. of EE Technical Report, 2002.
K. Eguro, S. Hauck, "Decipher: Architecture Development of Reconfigurable Encryption Hardware", University of Washington, Dept. of EE Technical Report UWEETR-2002-0012, 2002.
K. Compton, S. Hauck, "Track Placement: Orchestrating Routing Structures to Maximize Routability", University of Washington, Dept. of EE Technical Report UWEETR-2002-0013, 2002.
A. Sharma, C. Ebeling, S. Hauck, "PipeRoute: A Pipelining-Aware Router for FPGAs", University of Washington, Dept. of EE Technical Report UWEETR-2002-0018, 2002.
Z. Li, S. Hauck, "Don't Care Discovery for FPGA Configuration Compression" (PDF), 2002.
Z. Li, S. Hauck, "Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation", Technical Report, 2003.
Z. Li, K. Compton, S. Hauck, "Configuration Cache Management Techniques for Reconfigurable Computing", Technical Report, 2003.
K, Eguro, S. Hauck, "Issues of Wirelength Cost Models in Routing-Constrained FPGAs", University of Washington, Dept. of EE Technical Report UWEETR-2004-0006, 2004.
A. C. Miguel, A. R. Askew, A. Chang, S. Hauck, R. E. Ladner, E. Riskin, "Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation", Technical Report, 2004.
A. Sharma, K. Compton, C. Ebeling, S. Hauck, "Exploration of RaPiD-style Pipelined FPGA Interconnects", 2004.
Z. Li, S. Hauck, "Configuration Compression for Virtex FPGAs", Technical Report, 2004.
M. Haselman, M. Beauchamp, A. Wood, S. Hauck, K. Underwood, K. Scott Hemmert, "A Comparison of Floating Point and Logarithmic Number Systems for FPGAs", Technical Report, 2005.
A. Sharma, C. Ebeling, S. Hauck, "Architecture-Adaptive Routability-Driven Placement for FPGAs", 2006.
S. Hauck, K. Compton, K. Eguro, M. Holland, S. Phillips, A. Sharma, "Totem: Domain-Specific Reconfigurable Logic", 2006.
M. Holland, S. Hauck, "Domain-Specific Reconfigurable PAL/PLA Creation for SoC", 2007.
B. Ylvisaker, A. Carroll, S. Friedman, B. Van Essen, C. Ebeling, D. Grossman, S. Hauck, "Macah: A "C-Level" Language for Programming Kernels on Coprocessor Accelerators ", 2008.
M.D. Haselman, S. Hauck, T.K. Lewellen, R.S. Miyaoka, "Digital Pulse Timing in FPGAs for Positron Emission Tomography", Technical Report, 2008.