People > Faculty
David Allstot
 |
David Allstot Professor VLSI and Digital Systems M314 EE/CSE Box 352500 University of Washington Seattle, WA 98195 |
| Phone: (206) 221-5764 E-mail: allstot@ee.washington.edu |
University of California, Electrical Eng. and Computer Science,1979, Ph.D.
Oregon State University, Electrical and Computer Engineering, 1974, M.S.E.E.
University of Portland, Engineering Science, 1969, B.S.E.S.
Biosketch
David J. Allstot received the B.S.E.S. degree from the University of Portland in 1969, the M.S.E.E. degree from Oregon State University in 1974, and the Ph.D. degree from the University of California at Berkeley in 1979. He has held industrial positions with Tektronix, MOSTEK, and Texas Instruments, and academic positions with Oregon State, Carnegie Mellon, and Arizona State Universities. He became a Professor of Electrical Engineering at the University of Washington in 1999 and was appointed as the Boeing-Egtvedt Chair Professor of Engineering in 2000. He was appointed Acting Chair of Electrical Engineering in September 2004 and chair in May 2005. He has advised more than 80 M.S. and Ph.D. graduates. Dr. Allstot served as Editor of the IEEE Transactions on Circuits and Systems II and thrice as Guest Editor of the IEEE J. Solid-State Circuits. He was General Co-Chair of the 2002 IEEE International Symposium on Circuits and Systems. He is a Member of Eta Kappa Nu and Sigma Xi and a Fellow of IEEE.
Honors
IEEE W.R.G. Baker Award, 1980
Graduate Teaching Award, Dept. of Electrical Engineering, Souther Methodist University, 1982
Carter Award for Outstanding Teaching, College of Engineering, Oregon State University, 1988
Fellow of IEEE, 1992
Outstanding Undergraduate Teaching Award, Dept. of ECE, Carnegie Mellon University, 1993
Inventor Recognition Award, Semiconductor Research Corporation, 1994
Darlington Award, IEEE Circuits and Systems Society, 1995
Beatrice Winner Award, IEEE International Solid-State Circuits Conference, 1998
Best Project Award, NSF Center for the Design of Analog/Digital Integrated Circuits, 1999
Golden Jubilee Medal, IEEE Circuits and Systems Society, 1999
Outstanding Graduate Advisor Award, Dept. of Electrical Engineering, Univ. of Washington, 1999
ISSCC Service Award, IEEE International Solid-State Circuits Conference, 2000
Outstanding Service Award, IEEE Circuits and Systems Society, 2002
First-Place SiGe Design Competition, Semiconductor Research Corp., 2002
50-Year Anniversary Author Honor Roll, IEEE Intl. Solid-State Circuits Conference, 2003
Outstanding Panel Award, IEEE Intl. Solid-State Circuits Conference, 2003
Inventor Recognition Award, Semiconductor Research Corp., 2004
Outstanding Service Award, IEEE Intl. Sold-State Circuits Conference, 2004
Technical Achievement Award, IEEE Circuits and Systems Society, 2004
Inventor Recognition Award, Semiconductor Research Corp., 2005
Aristotle Award, Semiconductor Research Corp., 2005
Distinguished Engineer, Oregon State Univ. Engineering Academy, 2006
Research Interests
Analysis and design of RF/mixed-signal integrated systems; Design and computer-aided optimization of RF integrated circuits.
Current Projects:
Ultra Low-Voltage Analog/Digital Interfaces
CMOS RF Integrated Circuits for 2.4/5.6GHz Wireless Networks
Ultra Low-Voltage GHz Timing Generation/Recovery Techniques
CAD Synthesis/Optimization of CMOS RF Integrated CircuitsSystems-On-A-Chip Laboratory: http://analog.ee.washington.edu
Selected Publications
T. Kim, X. Li and D.J. Allstot, "Compact model generation for on-chip transmission lines," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 51, pp. 459-470, March 2004.
J.H. Park, K.Y. Choi and D.J. Allstot, "Parasitic-aware RF circuit design and optimization," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 51, pp. 1953-1966, Oct. 2004.
J. Guo, W. Law, W.J. Helms and D.J. Allstot, "Digital calibration for monotonic pipelined A/D converters," IEEE Trans. on Instrumentation and Measurement, vol. 53, pp. 1485-1492, Dec. 2004.
S.T. Lee, S.J. Fang, D.J. Allstot, A. Bellaouar, A.R. Fridi and P.A. Fontaine, "A quad-band GSM-GPRS transmitter with digital auto-calibration," IEEE J. Solid-State Circuits, vol. 39, pp. 2200-2214, Dec. 2004.
S.J. Fang, A. Bellaouar, S.T. Lee and D.J. Allstot, "An image rejection down-converter for low-IF receivers," IEEE Trans. on Microwave Theory and Techniques, vol. 53, pp. 478-487, Feb. 2005.
M. Chu and D.J. Allstot, "Elitist nondominated sorting genetic algorithm based RF IC optimizer," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, pp. 535-545, March 2005.
J. Paramesh, R. Bishop, K. Soumyanath and D.J. Allstot, "A four-antenna receiver in 90nm CMOS for beamforming and spatial diversity," IEEE J. Solid-State Circuits, vol. 40, pp. 2515-2524, Dec. 2005.
X. Li, S. Shekhar and D.J. Allstot, "Gm-boosted LNA and VCO Circuits in 0.18um CMOS," IEEE J. Solid-State Circuits, vol. 40, pp. 2609-2619, Dec. 2005.
Recent Conference Papers
S. Lee, S. Fang, D.J. Allstot, A. Bellaouar, A. Fridi and P. Fontaine, "A 1.5V 28mA fully-integrated fast-locking quad-band GSM/GPRS transmitter with digital auto-calibration in 130nm CMOS," IEEE Intl. Solid-State Circuits Conference, 2004, pp. 188, 189, 521.
H. Zarei and D.J. Allstot, "A low-loss phase shifter in 180nm CMOS for multiple-antenna receivers," IEEE Intl. Solid-State Circuits Conference, Feb. 2004, pp. 392, 393, 534.
J. Park and D.J. Allstot, "RF circuit synthesis using particle swarm optimization," IEEE Intl. Symposium on Circuits and Systems, May 2004, vol. V, pp. 93-96.
K. Choi, D.J. Allstot and V. Krishnamurthy, "A 900MHz fully-integrated GSM power amplifier in 250nm CMOS with breakdown voltage protection and programmable conduction angle," IEEE Radio Frequency IC Symposium, June 2004, pp. 369-372. (Outstanding Student Paper-Third prize)
G. Banerjee, D.T. Becher, C. Hung, D.J. Allstot and K. Soumyanath, "Measurement and modeling of noise parameters for desensitized low noise amplifiers," IEEE Custom IC Conference, Oct. 2004, pp. 387-390.
M. Chu and D.J. Allstot, "Elitist distributed particle swarm optimization: An algorithm for analog/RFIC optimization," Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 671-674.
J. Paramesh, R. Bishop, K. Soumyanath and D.J. Allstot, "A 1.4V 5GHz four-antenna Cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications," IEEE Intl. Solid-State Circuits Conference, Feb. 2005, pp. 210, 211, 594.
X. Li, S. Shekhar and D.J. Allstot, "Low-power gm-boosted LNA and VCO circuits in 0.18um CMOS," IEEE Intl. Solid-State Circuits Conference, Feb. 2005, pp. 534, 535, 615.
D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar, and K. Soumyanath, "Circuit techniques for CMOS multiple-antenna transceivers," IEEE Radio Frequency IC Symposium, June 2005, pp. 225-228. (Invited)
C.T. Peach, R. Bishop, A. Ravi, K. Soumyanath and D.J. Allstot, "A 9-b 400 Msample/s pipelined analog-to-digital converter in 90nm CMOS," European Solid-State Circuits Conference, Sept. 2005, pp. 535-538.
Books/Book Chapters
K.Y. Choi and D.J. Allstot, "Chapter 9: Parasitic-Aware RF IC Design and Optimization," in Wireless Communication Circuits and Systems, Y. Sun, Editor, IEE Circuits, Devices and Systems Book Publishers, London, pp. 215-244, 2003. ISBN: 0-85296-443-9
D.J. Allstot, K. Choi and J. Park, "Parasitic-aware Optimization of CMOS RF Circuits," Kluwer Academic Publishers, Boston, 184 pages, 2003. ISBN: 1-4020-7399-2
D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar, "Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits," in Design of High-Speed Communication Circuits, R. Harjani, Editor, World Scientific Publishing Company, 52 pages, 2006. ISBN 981-256-590-6
Patents
D.J. Allstot and S. Kiaei, "MOS Folded Source-Coupled Logic," U.S. Patent #5,149,992, Issued Sept. 22, 1992.
D.J. Allstot, G. Liang and H.C. Yang, "Current-Steering CMOS Logic Family," U.S. Patent #5,162,674, Issued Nov. 10, 1992.
D.R. Beck and D.J. Allstot, "Method and Apparatus for Double-Sampling a Signal," U.S. Patent #6,563,348 B1, Issued May 13, 2003.
K. Choi and D.J. Allstot, "Self-Bias and Digitally Tunable Conduction Angle Circuits for a Differential RF Non-Linear Power Amplifier Employing Low-Voltage Transistors," Filed Oct. 21, 2002. (pending).
Active Grants
Low Power, Low Noise RF and Mixed-Signal Circuit Design, Semiconductor Research Corporation
Low Voltage CMOS A/D Converter Techniques, NSF Center for the Design of Analog/Digital Integrated Circuits (CDADIC)
ITR/RC: Heterogeneous System Integration in System-on-a-Chip Designs, National Science Foundation.
Recent Graduate Students
Ph.D. Students
Douglas R. Beck, "An 8-b, 1.8 V, 20 MS/s Analog to Digital Converter," Ph.D. Dissertation, Univ. of Washington, June 12, 2002.
Kiyong Choi, "Parasitic-aware Design and Optimization of CMOS RF Power Amplifier," Ph.D. Dissertation, Univ. of Washington, July 21, 2003.
Jinho Park, "Fully-integrated CMOS Ultra-wideband Amplifier Design using Parasitic-aware Optimization Technique," Ph.D. Dissertation, Univ. of Washington, July 31, 2003.
Sher Jiun Fang, "CMOS Frequency Conversion Techniques for WCDMA," Ph.D. Dissertation, Univ. of Washington, August 15, 2003.
See Taur Lee, "Quad-band GMSK transmitter," Ph.D. Dissertation, Univ. of Washington, August 15, 2003.
Waisiu Law, "Digital Calibration of Non-Ideal Pipelined Analog-to-Digital Converters," Ph.D. Dissertation, Univ. of Washington, November 24, 2003.
Taeik Kim, "A CMOS Tunable Transmission Line Phase Shifter and Voltage-Controlled Oscillator for Wireless Communications," Ph.D. Dissertation, Univ. of Washington, March 1, 2004.
Xiaoyong Li, "Low Noise Design Techniques for Radio Frequency Integrated Circuits," Ph.D. Dissertation, Univ. of Washington, July 6, 2004.
Hossein Zarei, "Smart Antenna Phase Shift Network Architectures and Circuits," Ph.D. Dissertation, Univ. of Washington, Aug. 17, 2004.
Adam Chu, "Phase-Shifting Techniques for Wireless Beamforming Transmitter Applications," Ph.D. Dissertation, Univ. of Washington, Dec. 1, 2005.
Dicle Ozis, "Smart Antenna Transmitter Architectures and Circuits," Ph.D. Dissertation, Univ. of Washington, expected completion, March 2006.
Sankaran Aniruddanh, "Fast-Locking Phase-Locked Loop Techniques," Ph.D. Dissertation, Univ. of Washington, expected completion, March 2006.
Charles T. Peach, "Digital Calibration Techniques for Gb/s Analog-Digital Converters," Ph.D. Dissertation, Univ. of Washington, expected completion, June 2006.
Jeyanandh K. Paramesh, "Smart Antenna Receiver Architectures and Circuits in Fine-line CMOS Technology," Ph.D. Dissertation, Univ. of Washington, expected completion, June 2006.
Cameron Charles, Ph.D. student, passed general exam, expected comopletion, June 2006.
Gaurab Banerjee, Ph.D. student, passed general exam, expected comopletion, Dec. 2006.
Yi Tang, Ph.D. student, passed qualifying exam, exepected completion, Sept. 2007.
Nathan Neihart, Ph.D. student, passed qualifying exam, exepected completion, Sept. 2007.
Sudip Shekhar, Ph.D. student, passed qualifying exam, exepected completion, Sept. 2008.
Jeffrey S. Walling, Ph.D. student, passed qualifying exam, exepected completion, Sept. 2008.
M.S.E.E. Students
Robert M. Roze, "Class AB-D-G Line Driver for Central Office Asymmetric Digital Subscriber Line Systems," M.S.E.E. Thesis, Univ. of Washington, Aug. 14, 2001.
Jaynie Shorb, "A Resonant Pad Design for Narrowband Radio Frequency (RF) CMOS Applications," M.S.E.E. Thesis, Univ. of Washington, Aug. 15, 2002.
Adam Chu, "A Fully Integrated Quadrature LC Oscillator for Applications in the Unlicensed National Information-infrastructure Frequency Band," M.S.E.E. Thesis, Univ. of Washington, Oct. 3, 2002.
Sankaran Aniruddanh, "Low Phase-Noise CMOS Voltage-Controlled Oscillator Design using Lateral Bipolar Transistors," M.S.E.E. Thesis, Univ. of Washington, June 13, 2003.
Charles T. Peach, "A 200 Msample/s, 68dB SFDR, Double-Sampled, Pipelined Analog-to-Digital Converter in CMOS," M.S.E.E. Thesis, Univ. of Washington, Aug. 21, 2003.
Srinivas Kodali, "Multi-layered Inductor structures: Design, Modeling and Applications," M.S.E.E. Thesis, Univ. of Washington, March 17, 2004.
Kristen Neagle, "Design of a 10GHz CMOS Transmit/Receive Switch," M.S.E.E. Thesis, Univ. of Washington, July 28, 2004.
Sudip Shekhar, "Bandwidth Extension Techniques: Theory and Applications," M.S.E.E. Thesis, Univ. of Washington, March 15, 2005.
Allan Ecker, "Adaptive Online Calibration for MASH Sigma-Delta ADCs Using On-Chip Simulated Annealing," M.S.E.E. Thesis, Univ. of Washington, June 6, 2005.
Dan Nicholson, "Design Considerations for Highly Linear CMOS Low Noise Amplifiers," M.S.E.E. Thesis, Univ. of Washington, July 19, 2005.
Jeffrey S. Walling, "Theory and Application of Spiral Transformers for Silicon-based Integrated Circuits," M.S.E.E. Thesis, Univ. of Washington, July 25, 2005.
