Springbok is a rapid-prototyping system for board-level designs, and is described in "Springbok: A Rapid-Prototyping System for Board-Level Designs". The idea is to extend the orders of magnitude speed increase in ASIC logic emulation achieved by systems like Quickturn to the board level. Instead of mapping all logic to FPGAs, the system includes the actual chips into the mapping. The Springbok hardware includes baseplates that can be connected to form an arbitrarily large prototyping substrate. Daughter cards, with FPGAs on one side and arbitrary devices on the other, embed the user-specified devices into an FPGA-based routing structure. Extender cards are placed between the daughter cards and the substrate to add functionality and fix resource problems. Details on other multi-FPGA systems can be found in "The Roles of FPGAs in Reprogrammable Systems" and "Software Technologies for Reconfigurable Systems".
As part of developing the Springbok system, we have examined several issues related to multi-FPGA systems. In "Mesh Routing Topologies for Multi-FPGA Systems" we have done a quantitative study of nearest-neighbor routing topologies, and developed structures that greatly improve inter-FPGA routing efficiency.
In "Pin Assignment for Multi-FPGA Systems" we examined the problems of global routing in multi-FPGA systems, and proposed an algorithm for pin assignment for arbitrary FPGA topologies. The problem is that the global routing of FPGA systems will in general occur before the mappings in individual FPGAs have been placed. This means that the exact start and finish locations for inter-FPGA signals aren't fixed, and complete routing cannot be done by standard algorithms. The process of choosing intermediate FPGAs to route through can be handled by standard algorithms, so we concern ourselves in the paper with the issue of pin assignment - choosing what exact pins the routes will use. This is handled by placing all FPGAs simultaneously via force-directed placement, though spring-simplification rules based on physical laws make the problem manageable.
We have also considered the problem of partitioning for multi-FPGA systems. Two issues have been covered. First of all, there are a huge number of techniques that have been considered for partitioning. We performed a survey of many of them, primarily those that build from the Kernighan-Lin, Fiduccia-Mattheyses bipartitioning algorithm. The results of this survey is in "An Evaluation of Bipartitioning Techniques". We also considered the problem of how to apply bipartitioning iteratively to multi-FPGA systems. Specifically, it is important to figure out what order of cuts in the logic correspond to what locations in the multi-FPGA system, so we both know how many I/O resources are available, as well as picking the best order to optimize for locality, thus minimizing the length and amount of inter-FPGA routing. This work can be found in "Logic Partition Orderings for Multi-FPGA Systems". More details on all of our partitioning work can be found in our Logic Partitioning Page.
Finally, we examined the external interfaces of logic emulation systems. In "Achieving High-Latency, Low-Bandwidth Communication: Logic Emulation Interfaces" we described the problems of interfacing a logic emulation of a circuit, which will be running slower than the completed circuit, to an environment that requires certain logical and timing relationships. We show that these problems are significant, but they can be taken care of by a simple interface transducer. This transducer is made of FPGAs and memories, and can support most types of protocols. Also, the required mappings for this system can be created in a high-level language and automatically translated into FPGA logic.
Details of the entire Springbok project, as well as each of the topics discussed above, can be found in my thesis Multi-FPGA Systems.
1.) A small brown and white gazelle of southern Africa, that is capable of leaping high in the air.
2.) A popular jigsaw-puzzle company.
S. Hauck, G. Borriello, C. Ebeling "Mesh Routing Topologies for Multi-FPGA Systems" (PDF), IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 400-408, September, 199.
S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems" (PDF), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 9, pp. 956-964, September, 1997.
S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998.
S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems" (PDF), ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, February, 1995.
S. Hauck, G. Borriello, "An Evaluation of Bipartitioning Techniques" (PDF), Chapel Hill Conference on Advanced Research in VLSI, pp. 383-402, March, 1995.
S. Hauck, G. Borriello, C. Ebeling, "Mesh Routing Topologies for FPGA Arrays" (PDF), ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1994.
S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems (Extended Abstract)" (PDF), IEEE Workshop on FPGAs for Custom Computing Machines, pp. 11-13, April, 1994.
S. Hauck, G. Borriello, C. Ebeling, "Springbok: A Rapid-Prototyping System for Board-Level Designs" (PDF), 1995.
S. Hauck, A. Agarwal, "Software Technologies for Reconfigurable Systems" (PDF), 1996.