Triptych/Montage FPGA Architectures

Triptych and Montage are FPGAs designed with integrated routing and logic, and achieve higher densities than current commercial FPGAs.

Both FPGAs share the same overall routing structure. The basic fanin/fanout structure (a) is augmented with segmented routing channels (b) attached to a third RLB (Routing and Logic Block) input and output. The structure (c) is obtained by merging two copies of (b), with data flowing in opposite directions in the two copies. Shown in (d) are the connections between the two copies at diagonal crossings.

The RLB consists of 3 multiplexors for the inputs, a functional unit, 3 multiplexors for the outputs, and tristate drivers for the segmented channels. In Triptych, the functional unit is a 3-input lookup table (LUT), with an optional D-latch on it's output.

Montage has two different functional units. The most common (left) is similar to Triptych's, with a LUT and a D-Latch. The D-latch in Montage has a choice of two clocks to allow synchronous interfaces to be mapped, as well as a mode for initializing asynchronous stateholding functions. There is also a feedback line for implementing asynchronous stateholding functions. 1/16 of all functional units are arbiter blocks (right), which are capable of implemeting an arbiter, enabled arbiter, or synchronizer, with all inputs permuteable and invertable.



o Gaetano Borriello
o Steve Burns
o Carl Ebeling


Larry McMurchie

Graduate Students

o Darren Cronquist
o Scott Hauck
o David Song
o Elizabeth Walkup

Related Work

o Multi-FPGA Systems & Rapid-Prototyping
Development of the Springbok Rapid-Prototyping System for Board-Level Designs, as well as partitioning, pin assignment, and routing topology work for general multi-FPGA systems.
o Asynchronous Circuits
Survey of current asynchronous design methodologies, as well as the first FPGA for asynchronous circuits.

Journal Articles

S. Hauck, S. Burns, G. Borriello, C. Ebeling, "An FPGA For Implementing Asynchronous Circuits" (PDF), IEEE Design & Test of Computers, Vol. 11, No. 3, pp. 60-69, Fall, 1994.

G. Borriello, C. Ebeling, S. Hauck, S. Burns, "The Triptych FPGA Architecture" (PDF), IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 491-501, December, 1995.

C. Ebeling, L. McMurchie, S. Hauck, S. Burns, "Mapping Tools for the Triptych FPGA" (PDF), IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 473-482, December, 1995.

Patents, Theses, and Book Chapters

S. Hauck, G. Borriello, S. Burns, C. Ebeling, "Field-Programmable Gate Array for Synchronous and Asynchronous Operation", U.S. Patent 5,367,209, issued November 22, 1994.

Conference and Symposium Papers

S. Hauck, G. Borriello and C. Ebeling, "TRIPTYCH: An FPGA Architecture with Integrated Logic and Routing" (PDF), Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, pp. 26-43, March, 1992.

Workshop Papers

C. Ebeling, G. Borriello, S. Hauck, D. Song, and E. A. Walkup, "Triptych: A New FPGA Architecture" (PDF), Oxford Workshop on Field-Programmable Logic and Applications Oxford, September, 1991. Also appearing in W. Moore, W. Luk, Eds., FPGAs, Oxford: Abingdon EE&CS Books, pp. 75-90, 1991.

E. A. Walkup, S. Hauck, G. Borriello, and C. Ebeling, "Routing-directed Placement for the Triptych FPGA" (PDF), ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1992.

S. Hauck, G. Borriello, S. Burns and C. Ebeling, "Montage: An FPGA for Synchronous and Asynchronous Circuits" (PDF), 2nd International Workshop on Field-Programmable Logic and Applications, Vienna, August 1992. Also appearing in H. Grunbacher, R. W. Hartenstein, Eds., Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Berlin: Springer-Verlag, pp. 44-51, 1993.