People > Emeritus Faculty

Peter Lauritzen


Peter Lauritzen
Professor Emeritus
Power Electronics, Compact Device Modeling
M334 EE/CSE
Box 352500
University of Washington
Seattle, WA 98195
E-mail: plauritz@ee.washington.edu

Stanford University 1961 Ph.D.
Stanford University 1958 MS
California Institute of Technology 1956 BSEE


Biosketch

Peter O. Lauritzen is currently Professor Emeritus of Electrical Engineering at the University of Washington, having been an active faculty member from1965-1998. He icontinued to work part-time on compact modeling of power semiconductor devices from 2000 to 2007. From August to December 1999, he was Danfoss Professor at Aalborg University in Denmark. During the period 1983-98, he taught courses on analog electronics and devices and conducted research on compact model design. Many of the models aFrom this research came the lumped-charge technique for building compact models for power semiconductor devices, many of which are now on commercial simulators. From 1965 to 1978 semiconductor device noise, radiation effects, and device operation at cryogenic temperatures were his research areas.

For two years, 1979 - 1980, he was on-leave from the university as Engineering Manager of Avtech Corporation, Seattle, WA. From 1961 to 1965 he was a Member of the Technical Staff working on semiconductor device research and development at Fairchild Semiconductor Division, Palo Alto, CA.

Peter O. Lauritzen was born in Valparaiso, IN, USA on February 14, 1935. He received the BS degree from the California Institute of Technology, and the MSEE and Ph.D. degrees from Stanford University, all in electrical engineering in 1956, 1958, and 1961, respectively.

He was Conference Chair for IEEE PESC'93.

Honors

Aug.-Dec. 1999 Danfoss Visiting Professor, Aalborg University, Denmark
July-Dec. 1997 Fulbright Senior Lecturer, Indian Institute of Technology, Madras, India,
1974 NASA-ASEE Faculty System Design Award

Research Interests

Compact modeling of semiconductor devices, partcularly power electronic devices. See the Table of Signficant Compact Models developed from 1990-2004, most of which are available for downloading as well as papers on power semiconductor models.

Selected Publications

P.O. Lauritzen, H.A. Mantooth, "Compact models of power devices and power ICs for circuit simulation", PASSWORD (Shindengen Electric Mfg. Co, LTD), Vol. 10, Nov. 1988. A Japanese translation is also available. A revised version was published as a PSMA, Power Sources Manufacturing Assn., Power Semiconductor Committee Report, in March 2000.

C.L.Ma, P.O.Lauritzen, J.Sigg, "Modeling of Power Diodes with the Lumped-Charge Modeling Technique", IEEE Transactions on PowerElectronics, Vol. 12, No. 3, pp. 398-405, May 1997

I. Budihardjo, P. O. Lauritzen, H.A. Mantooth, "Performance Requirementsfor Power MOSFET Models", IEEE Transactions on Power Electronics, Jan 1997

I. Budihardjo, P.O. Lauritzen, "The Lumped-Charge Power MOSFET Model, Including Parameter Extraction", IEEE Transactions on Power Electronics, May 1995

C.L. Ma & P.O. Lauritzen, "A Simple Power Diode Model with Forward and Reverse Recovery", IEEE Transactions on Power Electronics, Vol. 8, No.4, October 1993.

P.O.Lauritzen & C. L. Ma, "A Simple Diode Model with Reverse Recovery", IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991.

Select Conference Papers

P.O. Lauritzen, G. K. Andersen, M. Helsper, A Basic IGBT Model with Easy Parameter Extraction, IEEE Power Electronics Specialists Conf, Vancouver, BC, Canada, June 2001.

Y. Subramanian, P.O. Lauritzen and K.R. Green,"A Compact Model for an IC Lateral Diffused MOSFET Using the Lumped-Charge Methodology", MSM99, San Juan, PR, April 1999

Y. Subramanian, P.O. Lauritzen and K.R. Green, "Two lumped-charge based power MOSFET models", Proc. of IEEE PELS Workshop on Computers in Pwr. Elec., Como, Italy, July 1998.

K.Y.Wong, P.O. Lauritzen, S.S. Venkata, A. Sundaram, R. Adapa, "An SCR/GTO Model Designed for a Basic Level of Model Performance", IEEE IAS Annual Meeting, October 1996.

B. Fatemizadeh, P.O. Lauritzen, "An Analytical Model of Power Bipolar Transistor for Circuit Simulation", IEEE PELS Workshop on Computers in Power Electronics, Portland, OR, August 1996.

B. Fatemizadeh, P.O. Lauritzen, D. Silber, “Modeling of Power Semiconductor Devices, Problems, Limitations and Future Trends”, IEEE PELS Workshop on Computers in Power Electronics, Portland, OR, August 1996

N. Talwalkar, P.O. Lauritzen, B. Fatemizadeh, D. Perlman, C.L. Ma, "A Power BJT for Circuit Simulation", IEEE PESC, Baveno, Italy, June 1996

Books

R. Heeren, P.O. Lauritzen, "Compendium on Teaching Techniques in Engineering Education and a Lifetime of Learning," American Society for Engineering Education Monograph (with 18 other faculty in a NASA/ASEE Engineering SystemsDesign Workshop), ASEE Publication, 1975

Patents

P.O.Lauritzen, "Transistor Structure with Steep Impurity Gradients Having FastTransition Between the Conducting and Nonconducting State", U.S. Patent No.3,463,972, issued August 26, 1969.

P.O. Lauritzen, C.E. Boucher, "Current Stabilizer Circuit for ThermionicElectron Emission Device", U.S. Patent No. 3,567,995, issued March 2, 1971.

H.P. Yee, P.O. Lauritzen, S.S. Yee, "Majority Carrier Power Diode", US patent No. 5,510,641, issued April 22, 1996

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