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Visvesh Sathe


Dr. Visvesh Sathe
Assistant Professor
Energy-efficient VLSI design. Circuit and system optimization. Clocking
M314 EEB
Box 352500
University of Washington
Seattle, WA 98195
Phone: (206) 543-7635
E-mail:

University of Michigan, Ann Arbor, Ph.D 2007
University of Michigan, Ann Arbor, MS 2004
Indian Institute of Technology, Bombay, B.Tech 2001


Biosketch

Visvesh Sathe joined the University of Washington Department of Electrical Engineering in 2013. Prior to joining the faculty at the University of Washington, he served as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD, where his research focused on inventing and developing new technologies for next-generation microprocessors. Dr. Sathe has led the research and development effort at AMD that resulted in the first-ever resonant clocked commercial microprocessor. In addition, several of his other inventions have been adopted for use in future-generation microprocessors. His doctoral thesis was selected as the best dissertation in EECS for 2007 and was nominated for the Rackham Graduate School Distinguished Dissertation Award at the University of Michigan. He is a member of the Technical Program Committees of the Custom Integrated Circuits Conference and the International Symposium on Quality Electronic Design

Teaching

Fall 2013: EE 538A: Special Topics in VLSI Design

Fall 2014: EE 476: Introduction to VLSI Design

Winter 2015: EE 477: VLSI 1

Spring 2015: EE 526: VLSI 2

Research Interests

I am interested in understanding and solving problems facing the design of efficient integrated circuits (ICs) and systems over a broad range, from ultra-low power chips to high-performance microprocessors. The end of Dennard scaling has resulted in a "levelling-off" of single-threaded performance in digital systems. It has also ushered in an era of stark trade-offs between performance, energy dissipation, variability and reliability. My group is exploring solutions toward building novel and innovative systems at the intersection of architecture, low-power VLSI and mixed-signal design. Below is a brief description of some of these areas.

1. Clocking. Clocking continues to be a crucial aspect of designing integrated circuits of a high quality, we are currently looking at efficient clock-domain crossing techniques, next generation clock distribution architectures, and frequency-scalable resonant clocking.

2. Energy-efficient communication. Scaling has provided substantial computational efficiencies in ICs. The problem of increasingly dissipative communication on large chips, many-core chips, and in the interaction of the IC with the physical world is becoming more prominent. A variety of circuit techniques seeking to minimize the Joules-per-bit in communication have been previously employed. We are exploring VLSI circuit and architecture techniques to instead minimize the "joules-per-information" in such communication, thereby achieving more energy-efficient communication.

3. Adaptive circuits and architectures. Future systems-on-chip are likely to consist of a variety of cores, accelerators, memories employing heterogeneous 3D integration. Design time optimization is becoming increasingly un-tenable. My group is looking at a variety of adaptive circuit and system strategies to enable runtime adaptation of silicon to effectively meet runtime requirements. A particularly interesting application of this work is the the area of wireless sensor nodes where interdependencies between power conversion and regulation, processing, memory and communication allow opportunities for creative cross-boundary system adaptation.

Selected Publications

V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, S. Naffziger, “Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor,” Journal of Solid-State Circuits, Invited paper, Special Issue on ISSCC ‘12, vol. 48, no. 1, pp 140-149. Jan. 2013.

W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou, “187MHz subthreshold-supply charge-recovery FIR,” IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on 2009 Symposium on VLSI Circuits, vol. 45, no. 4, pp. 793-803, Apr. 2010.

V. S. Sathe, J. Kao and M. C. Papaefthymiou, “Resonant-clock latch-based design,” IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on 2007 Symposium on VLSI Circuits, vol. 43, no. 4, pp. 864-873, Apr. 2008.

V. S. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou, “Energy-efficient GHz-class charge-recovery logic,” IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on ISSCC ‘06, vol. 42, no. 1, pp. 38-47, Jan. 2007.

Selected Conference Papers

V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. Papaefthymiou and S. Naffziger, “Resonant clock design for a power-efficient, high-volume x86-64 microprocessor,” in IEEE Int. Solid-State Circuits Conference, pp. 68-69 San Francisco, CA, Feb. 2012. An extended version of this paper was invited for publication in the IEEE Journal of Solid-State Circuits, Special Issue on ISSCC‘12.

H.-P. Le, M. Seeman, S. Sanders, V. S. Sathe, S. Naffziger, and E. Alon, “A 32nm fully-integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 77% efficiency,” in IEEE Int. Solid-State Circuits Conference, pp. 210-211, San Francisco, CA, Feb. 2010.

J. C. Kao, W. S. Ma, V. S. Sathe, and M. C. Papaefthymiou, “A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead,” in IEEE European Solid-State Circuits Conference(ESSCIRC), pp. 160-163, Athens, Greece, Sep. 2009.

M. C. Papaefthymiou, A. Ishii, J. Kao., and V. S. Sathe, “A resonant-clock 200MHz ARM926EJ-S microcontroller,” in IEEE European Solid-State Circuits Conference(ESSCIRC), pp. 356-359, Athens, Greece, Sep. 2009.

W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou, “A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic,” in IEEE Symposium VLSI Circuits, pp. 202-203, Kyoto, Japan, Jun. 2009. An extended version of this paper was invited for publication in the IEEE Journal of Solid-State Circuits, Special Issue on VLSI Circuits‘09.

V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou, “RF2: A 1GHz FIR filter with distributed resonant clock generator,” in IEEE Symposium VLSI Circuits, pp. 44-45, Kyoto, Japan, Jun. 2007. An extended version of this paper was invited for publication in the IEEE Journal of Solid-State Circuits, Special Issue on VLSI Circuits‘07.

V. S. Sathe, J-Y. Chueh, and M. C. Papaefthymiou, “A 1.1GHz charge-recovery logic,” in IEEE Int. Solid-State Circuits Conference, pp. 1540-1549, San Francisco, CA, Feb. 2006. An extended version of this paper was invited for publication in the IEEE Journal of Solid-State Circuits, Special Issue on ISSCC&lsquo06.

V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou, “A 0.8-1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 583-586, San Jose, CA, Sep. 2007.

J.-Y. Chueh, V. S. Sathe, and M. C. Papaefthymiou, “900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading,” in Proc. IEEE Custom Integrated Circuits Conference(CICC), pp. 777-780, San Jose, CA, Sep. 2006.

Patents

V. S. Sathe and S. Naffziger, “Method to safely transition from resonant clocked mode to conventional clocked mode” submitted to US Patent and Trademark Office, Jul. 2012.

V. S. Sathe, S. Naffziger, “Method of dynamically optimizing the impedance of a resonant clock switch”, submitted to US Patent and Trademark Office, Jul. 2012.

V. S. Sathe, S. Arekapudi, C. Ouyang and K. Viau, “Method of safely entering and existing resonant clocking mode”, submitted to US Patent and Trademark Office, Jul. 2012.

V. S. Sathe and S. Naffziger “Method for programmable clock drive in digital circuits”, submitted to US Patent and Trademark Office, Jul. 2012.

V. S. Sathe, S. Naffziger and S. Arekapudi “Method to implement resonant clock driver for frequency-scalable systems”, submitted to US Patent and Trademark Office, Jul. 2012.

V. S. Sathe, S. Naffziger and S. Pant, “Clock stretcher for voltage droop mitigation,” submitted to US Patent and Trademark Office, Jan. 2011.

V. S. Sathe and S. Naffziger, “Oscillator device and method thereof,” submitted to US Patent and Trademark Office, Dec. 2010.

V. S. Sathe, S. Naffziger, and S. Arekapudi, “Sense amplifier monotizer”, submitted to US Patent and Trademark Office, Dec. 2010.

S. Kosonocky, S. Naffziger, and V. S. Sathe “Interposer including voltage regulator and method thereof, ” US Patent Application 2010/0072961 Sep. 23, 2008.

J-Y. Chueh, J. Kao, V. S. Sathe, and M. C. Papaefthymiou, “Clock distribution network architecture with clock skew management,” US Patent 7 956 664, 3 Dec. 2007.

J-Y. Chueh, J. Kao, V. S. Sathe, and M. C. Papaefthymiou, “Clock distribution network architecture for resonant-clocked systems,” US Patent 7 719 316, 3 Dec. 2007.

J-Y Chueh, J. Kao, V. S. Sathe, and M. C. Papaefthymiou, “Clock distribution network architecture with resonant clock gating,” US Patent 7719 317, 3 Dec. 2007 .

M. C. Papaefthymiou, V. S. Sathe, and C. H. Ziesler, “Energy recovery boost logic,” US Patent 7 355 454, 15 Jun 2005.


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