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Visvesh Sathe

  • Assistant Professor

Visvesh Sathe joined the University of Washington Department of Electrical Engineering in 2013. Prior to joining the faculty at the UW, he served as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD, where his research focused on inventing and developing new technologies for next-generation microprocessors. Sathe led the research and development effort at AMD that resulted in the first-ever resonant clocked commercial microprocessor. In addition, several of his other inventions have been adopted for use in future-generation microprocessors. His doctoral thesis was selected as the best dissertation for 2007 in electrical engineering and computer science at the University of Michigan, Ann Arbor, and was also nominated for the university’s Rackham Graduate School Distinguished Dissertation Award.

Sathe’s group conducts research over a variety of areas covering circuits and architectures for low power computing and biomedical systems.  He serves as a member of the Technical Program Committees of the Custom Integrated Circuits Conference and has previously served as a guest editor for the Journal of Solid-State Circuits.

Research Interests

  • Ultra low-power biomedical sensing, recording and computation
  • Next generation clocking architectures for computing and communication
  • Supply conversion, distribution and regulation

Representative Publications

  • V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, S. Naffziger, “Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor”, IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on ISSCC ‘14, vol. 48, no. 1, pp. 140–149, Jan. 2013.
  • S.K. Shin, J.C. Rudell, D.C. Daly, C.E. Muñoz, D.Y. Chang, K. Gulati, H.S. Lee and M.Z. Straayer, “A 12-bit 200 MS/s Zero-Crossing-Based Pipelined ADC with Early sub-ADC Decision and Output Residue Background Calibration,” Proc. IEEE J. Solid-State Circuits,” vol. 49, pp. 1366-1382, Jun., 2014.
  • V. S. Sathe, “Quasi-Resonant Clocking : A Run-time Control Approach for True Voltage-Frequency-Scalability,” IEEE ISLPED, La Jolla, 2014.
  • V. S. Sathe, Jae-sun Seo “Analysis and Optimization of CMOS Switched-Capacitor Voltage Converters,” IEEE ISLPED, Rome, Italy 2015
  • F. Rahman and V. S. Sathe, “Voltage-Scalable Frequency Independent Quasi-Resonant Clocking Implementation of a 0.7–1.2V DVFS System”, ISSCC 2016
  • W. A. Smith, B. Mogen, E. Fetz, V. S. Sathe and B. Otis, “Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 μW Analog Front End with Reduced ADC Resolution Requirements”, to appear in Transactions in Biomedical Circuits and Systems 2016
Visvesh Sathe Headshot
Phone206-543-7635
sathe@uw.edu
Web PageClick Here
Mail
M314 EEB

Research Labs

Research Areas

Education

  • Ph.D. Electrical Engineering, 2007
    University of Michigan, Ann Arbor
  • M.S. Electrical Engineering, 2004
    University of Michigan, Ann Arbor
  • B.S. Technology, 2001
    Indian Institute of Technology, Bombay