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Biologically Inspired Devices and Systems For Integrated Electronics

Within the next ten to twenty years, the theoretical limits of photolithography-defined circuits will be reached. As device dimensions shrink, it is no longer simply a matter of packing more transistors into a smaller space. The move requires a fundamental change in the computational paradigm, as any device will necessarily have to cope with, but more likely exploit, the quirky behavior of nanoscale systems. With the increase in device density comes the necessity to design massively parallel and inherently fault-tolerant systems. These systems will be based on newly discovered physical phenomena, and as a result will require new design automation and fabrication technologies. In other words, the move to the nano-realm will require more than just a physical mechanism; it will require a complete infrastructure. Given this requirement, it is advantageous to design hybrid systems cable of exploiting novel physical phenomena while utilizing the existing microelectronics manufacturing backbone. We are specifically interested in using biological systems as a guide to designing these new computational structures, from both the device and systems point of view.

For more information you can contact Alex Nugent

New Techniques for Jitter Measurement

With the increase of GHz technology today, jitter requirements of circuits such as the Phase Locked Loop (PLL) have become stringent, in the order of a few picoseconds. This measurement resolution significantly increases the cost of jitter measurement during the test stage. Due to this demand for state of the art jitter measurement techniques, our research in this area is focused on BIST (Built-In Self-Test) methods of measurement, which has the following considerations:

For more information you can contact Hieu Nguyen or David Bordoley

Method for Testing High Frequency Mixed-Signal Telecommunication System

Deep sub-micron technology enables the developing of SoC (System-On-Chip) and increasing the work frequency of IC system. While the exponential increase (according to Moore's Law) in capabilities has come to seem inevitable, daunting challenges must be overcome at all levels of design and test to allow these advances to continue.

Testing of GHz mixed analog/RF/digital systems is a significant challenge, potentially consuming well more than halt of the overall designer effort. So it's very necessary to create and validate new scalable test methodology for GHz mixed analog/RF/digital systems to decrease the design cycle and lower the testing cost.

Our recent focus is on the measurement of key performance parameters such as delay, jitter, phase noise, BER, etc.

For more information you can contact Qi (Stephen) Wang

Method for Testing High Frequency Mixed-Signal Telecommunication System

The research focuses on finding testability measurements techniques and Automatic Test Pattern Generation (ATPG) methodology for an analog or mixed signal (AMS) block imbedded in a chip. The basic idea is testing the functionality and evaluating the performance of the circuitry of such a block, while there are multiple analog and digital signal paths from tester's probes to the block's input/output pins.

For more information you can contact Kianosh Rahimi