M. Soma, "Fault modeling techniques for
mixed-signal circuits and
systems," accepted to appear in Special Issue on VLSI Testing Toward
21st Century, ed. K. Kinoshita, Integration: The VLSI Journal,
Elsevier, Dec. 1998
G. Devarayanadurg and M. Soma, "Design and test of hybrid integrated circuits," accepted to appear in Encyclopedia of Electrical and Electronics Engineering, ed. J. G. Webster, 1998.
Y. Lim and M. Soma, "Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits", IEEE Trans. VLSI Syst., vol. 5, no. 3, Sept. 1997.
K. Son and M. Soma, "Dynamic life-estimation of CMOS ICs in real operating environment: Precise electrical method and MLE," IEEE Trans. Reliability, vol. 46, no. 1, pp. 31-38, March 1997.
H.-J. Park and M. Soma, "Analytical model for switching transitions of submicron CMOS logic," IEEE J. Solid State Circuits, pp. 880-889, June 1997.
G. Devarayanadurg and M. Soma, "Design and test of hybrid integrated circuits," accepted to appear in Encyclopedia of Electrical and Electronics Engineering, ed. J. G. Webster, 1998.
Y. Lim and M. Soma, "Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits", IEEE Trans. VLSI Syst., vol. 5, no. 3, Sept. 1997.
K. Son and M. Soma, "Dynamic life-estimation of CMOS ICs in real operating environment: Precise electrical method and MLE," IEEE Trans. Reliability, vol. 46, no. 1, pp. 31-38, March 1997.
H.-J. Park and M. Soma, "Analytical model for switching transitions of submicron CMOS logic," IEEE J. Solid State Circuits, pp. 880-889, June 1997.
Recent Conference Papers
T.J Yamaguchi, M. Soma, M. Ishida, T.
Watanabe, and T. Ohmi,
"Extraction of Peak-to-peak and RMS Sinusoidal Jitter using an Analytic
Signal Method," in IEEE VLSI Test Symposium, May 2000, pp.395-402,
Montreal, Quebec, Canada.
S. Kim, M. Soma and D. Risbud, "An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops," in IEEE VLSI Test Symposium, May 2000, pp.231-236, Montreal, Quebec, Canada.
S. Kim et al., "Automatic Analog Test Signal Generation Using Multifrequency Analysis," in Trans. on Circuits and Systems, May 1999 pp.565-576
M. Soma, "Testing challenges in deep submicron ICs," IEEE 3rd Int. Mixed-signal Test Workshop, June 9-11, 1998, The Hague, Holland.
B. Kaminska, K. Arabi, I. Bell, P. Goteti, J.L. Huertas, B. Kim, A. Rueda, and M. Soma, "Analog and mixed-signal benchmark circuits First release," in Proc. IEEE International Test Conf., Nov. 3-6, 1997, Washington, DC.
Y. Takahiro and M. Soma, "Dynamic testing of ADCs using wavelet transforms," in Proc. IEEE International Test Conf., Nov. 3-6, 1997, Washington, DC.
M. Soma, T. M. Bocek, T.D. Vu, and J.D. Moffatt, "Experimental results for current-based analog scan," in Proc. IEEE International Test Conf., Nov. 3-6, 1997, Washington, DC.
K.-I. Son, H.-J. Park, and M. Soma, "A top-down design of analog circuits using multi-class classifiers as a topology selector," in Proc. 5th Int. Conf. VLSI & CAD, Oct. 13-15, 1997, Seoul, Korea.
S. Kim, M. Soma and D. Risbud, "An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops," in IEEE VLSI Test Symposium, May 2000, pp.231-236, Montreal, Quebec, Canada.
S. Kim et al., "Automatic Analog Test Signal Generation Using Multifrequency Analysis," in Trans. on Circuits and Systems, May 1999 pp.565-576
M. Soma, "Testing challenges in deep submicron ICs," IEEE 3rd Int. Mixed-signal Test Workshop, June 9-11, 1998, The Hague, Holland.
B. Kaminska, K. Arabi, I. Bell, P. Goteti, J.L. Huertas, B. Kim, A. Rueda, and M. Soma, "Analog and mixed-signal benchmark circuits First release," in Proc. IEEE International Test Conf., Nov. 3-6, 1997, Washington, DC.
Y. Takahiro and M. Soma, "Dynamic testing of ADCs using wavelet transforms," in Proc. IEEE International Test Conf., Nov. 3-6, 1997, Washington, DC.
M. Soma, T. M. Bocek, T.D. Vu, and J.D. Moffatt, "Experimental results for current-based analog scan," in Proc. IEEE International Test Conf., Nov. 3-6, 1997, Washington, DC.
K.-I. Son, H.-J. Park, and M. Soma, "A top-down design of analog circuits using multi-class classifiers as a topology selector," in Proc. 5th Int. Conf. VLSI & CAD, Oct. 13-15, 1997, Seoul, Korea.