Intelligent Systems Laboratory
Proteus Project
The goal of this large multi-year project is to design and build an image processing
system having a reconfigurable fault tolerant pipeline network architecture
and capable of a peak processing rate of at least 10 gigaflops. The design will
involve 256 processors of the Intel 80860 class processor or equivalent. Each
processor will have separate local memory for image data and instructions and
each group of four processors will have a shared memory. The operations supported
by the system will include mathematical morphology, convolution, connected
component analysis, and pattern classification. It will be able to be used for
real time processing of images from vision guided robot assembly and inspection.
