UWEE Foldy-Lax Via Tool

Fast Full-wave 3D Electromagnetic Modeling of Massively-coupled Multiple Vias in Multilayered Electronic Packaging

Patent

  1. L. Tsang et al, Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures, US Patent No. 7149666, filed on May 30, 2002, granted on Dec. 12, 2006.   [Google Patent Search]

Selected Publications

  1. L. Tsang, H. Chen, C.-C. Huang, and V. Jandhyala, "Modeling of multiple scattering among vias in planar waveguides using Foldy-Lax equations," Micro. Opt. Technol. Lett., vol. 31, no. 3, pp. 201-208, Nov. 2001.

  2. C.-C. Huang, L. Tsang, and C.H. Chan, "Multiple scattering among vias in lossy planar waveguides using SMCG method," IEEE Trans. Advanced Packaging, vol. 25, no. 2, pp. 181-188, May 2002.

  3. H. Chen, Q. Lin, L. Tsang, C.-C. Huang, and V. Jandhyala, "Analysis of a large number of vias and differential signaling in multilayered structure," IEEE Trans. Microwave Theory Tech., vol. 51, no. 3, pp. 818-829, Mar. 2003.

  4. L. Tsang and D. Miller, "Coupling of vias in electronic packaging and printed circuit board structures with finite ground plane," IEEE Trans. Advanced Packaging, vol. 26, no. 4, pp. 375-384, Nov. 2003.

  5. C.-C. Huang, L. Tsang, C.H. Chan, and K.-H. Ding, "Multiple scattering among vias in planar waveguides using preconditioned SMCG method," IEEE Trans. Microwave Theory Tech., vol. 52, no. 1, pp. 20-28, Jan. 2004.

  6. C.-J. Ong, D. Miller, L. Tsang, B. Wu, and C.-C. Huang, "Application of the Foldy Lax multiple scattering method to the analysis of vias in ball grid arrays and interior layers of printed circuit boards," Micro. Opt. Technol. Lett., vol. 49, no. 1, pp. 225-231, Jan. 2007.

  7. C.-J. Ong, B. Wu, L. Tsang and X. Gu, "Full-wave solver for microstrip trace and through-hole via in layered media," IEEE Trans. Adv. Pkg., vol. 31, no. 2, pp. 292-302, May 2008.

  8. B. Wu and L. Tsang, "Modeling multiple vias with arbitrary shape of antipads and pads in high speed interconnect circuits," IEEE Microwave and Wireless Comp. Lett., vol. 19, no. 1, pp. 12-14, Jan. 2009.

  9. B. Wu and L. Tsang, "Signal integrity analysis of package and printed circuit board with multiple vias in substrate of layered dielectrics," IEEE Trans. Advanced Packaging, vol. 33, no. 2, pp. 510-516, May 2010.

  10. B. Wu, X. Gu, L. Tsang and M. B. Ritter, "Electromagnetic Modeling of Massively Coupled Through Silicon Vias for 3-D Interconnects," Micro. Opt. Technol. Lett., vol. 53, no. 6, pp. 1204-1206, Jun. 2011.

New Functions in Current Version 2.3

  1. Layout the vias in random positions
  2. Vary the size of via, pad and void
  3. Model the pad and void in circular or square shape
  4. Model the vias with off-center drilling
  5. Model the vias in the multilayered stackup
  6. Assign different materials with dielectric loss
  7. Assign the GND vias apart from signal vias
  8. Model via pair in shared void for differential signaling
  9. Provide mixed mode co-channel S-parameters
  10. Control the simulation frequency range and step size
  11. Provide GUI for vias drawing and ports labeling
  12. Include high order waveguide modes and cylindrical harmonics
  13. Provide command line (DOS) version for quick access
  14. Control the simulation time and memory usage
  15. Produce S/Y parameter results in the touchstone format
  16. Plot S/Y parameters and give comparison for different ports
  17. Import structure profile and export plots with specified names

Version 2.3 User Manual (PPT in PDF format) Download

CPU Report within 5% Accuracy

    The reported CPUs for single layer problem are taken from actual simulation for 20 frequency points on Intel Xeon Qualcore 3.0 GHz with 13GB RAM.

Helps on GUI

  1. Profile Path: Save the profile of specified name in the same folder as the exe file

  2. Results Path: Save the results data file of specified name in the same folder as the exe file

  3. X Number: Size of via array in the X direction [integer and scalar]

  4. Y Number: Size of via array in the Y direction [integer and scalar]

  5. X Step: Step size of via array in the X direction [scalar or vector] (For vector input: separate with blank only)

  6. Y Step: Step size of via array in the Y direction [scalar or vector]

  7. Unit: 1 mil = 0.0254 mm, 1 um (micron) = 0.001 mm

  8. Radius of Via, Pad and Void [scalar only]

  9. Via-pad only at via terminals (exterior layer) or at every layer [selection]

  10. Via Off-center Drilling [scalar only]

  11. X offset: Array offset along the X direction [scalar or vector]

  12. Back / Forth: Array offset along the X direction in a stagger way [selection]

  13. Forward: Array offset along the X direction like a stairway [selection]

  14. Layers: Number of layers in the package [integer and scalar]

  15. Thickness: Thickness of each layer starting from bottom [scalar or vector]

  16. Dielectric Constants: Dielectric constant of substrate at each frequency point [scalar or vector]

  17. Loss Tangent: Loss tangent of substrate at each frequency point [scalar or vector]

  18. Via Number in Adjustment Option: The number of labelled via for the position adjustment [integer only] [scalar or vector]

  19. X in Adjustment Option: The movement of chosen via along the X direction [scalar or vector]

  20. Y in Adjustment Option: The movement of chosen via along the Y direction [scalar or vector]

  21. Absolute in Adjustment Option: The new position uses the coordinate originated at zero

  22. Relative in Adjustment Option: Move the via from the original position of the via

  23. Input and Output Ports in the Plot Window: The vector of output ports has the one-to-one relationship with that of the input ports [integer only] [scalar or vector]

Contact

    Inventor: Professor Leung Tsang

    Technical Support: Xin Chang

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