IPRAIL: Analog Layout Automation

PI | Students | Sponsors | Publications

Principal Investigator

Richard Shi

Participating Students:

Nuttorn Jangkrajarng
Sam Bhattacharya
Roy Hartono
Youcef Bourai

NSF ITR Program

• S. Bhattacharya, N. Jangkrajarng, and C.-J. R. Shi, "Multi-level symmetry constraint generation for retargeting large analog layouts," IEEE Trans. on Computer-Aided Design, Accepted and in press.
• N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.-J. R. Shi, "IPRAIL: Intellectual property reuse based analog IC layout automation," Integration, the VLSI Journal, vol. 36, no. 4, pp. 237-262, Nov. 2003.
• S. Bhattacharya, N. Jangkrajarng, and C.-J. R. Shi, "Template-driven parasitic-aware optimization of analog integrated circuit layouts", IEEE/ACM Design Automation Conf., June 2005 (154 out of 735 accepted).
• R. Hartono, N. Jangkrajarng, S. Bhattacharya, and C.-J. R. Shi, "Automatic device layout generation for analog layout retargeting", pp. 457-462 in Proc. International Conf. on VLSI Design, Jan. 2005.
• S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C.-J. R. Shi, "Challenges and techniques for layout automation of radio-frequency integrated circuits", in Proc. Asia Pacific Microwave Conf. (APMC'04), Dec. 2004.
• S. Bhattacharya, N. Jangkrajarng, R. Hartono, C.-J. R. Shi, "Correct-by-construction layout-centric retargeting of large analog designs", pp. 139-144 in Proc. IEEE/ACM Design Automation Conf. (DAC'04), June 2004.
• *S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C.-J. R. Shi, "Hierarchical extraction and verification of symmetry constraints for analog layout automation," pp. 400-405 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04) , Japan, Jan. 2004 (148 out of 291 accepted).
• N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.-J. R. Shi, "Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting," pp. 394-399 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).
• *N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.-J. R. Shi, "Automatic analog layout resizing for process and performance retargeting," pp. 704-707 in Proc. IEEE International Symp. on Circuits and Systems (ISCAS'03), vol. 4, May 2003.
• Y. Bourai and C.-J Shi, ``Layout compaction for yield optimization via critical-area minimization", Proc. Design, Automation and Test in Europe Conference (DATE'00), Paris, France, March 2000.
• Y. Bourai and C.-J. Shi, ``Symmetry detection for analog layout recycling", pp. 5-7 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 18-21, 1999.

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