Communication VLSI Circuit
Implementation: Low Density Parity Check (LDPC) Code Decoder
Eric Normark (now with Department of Defense)
L. Yang, H. Liu, and C.-J. R. Shi, "Construction and FPGA implementation of low-error-floor multi-rate low-density parity-check code decoders",
IEEE Trans. on Circuits and Systems-I, in press.
L. Yang, H. Liu and C.-J. R. Shi, "A cycle elimination method for constructing VLSI-oriented LDPC codes",
IEEE 62nd Vehicle Technology Conf., Dallas, TX, USA, September 25 to 28, 2005. Accepted (625 out of 1084 accepted).
L. Yang, M. Shen, H. Liu and C.-J. R. Shi, ``An FPGA implementation of low-density parity-check code decoder with multi-rate capability", pp. 760-763 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'05), Shanghai, China, Jan. 2005 (177 out of 692 accepted).
Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, and C.-J. Richard Shi, "A High-Throughput Low-Power Fully Parallel 1024-bit ½ Rate Low Density Parity Check Code Decoder in 3-Dimensional Integrated Circuits", Accepted by
Asia and South Pacific Design Automation Conf. (ASPDAC'06),
Japan, Jan 2006.
*L. Yang, H. Liu and C.-J. R. Shi, "VLSI implementation of low-error-floor and capacity-approaching performance low-density parity-check codes with multi-rate capacity",
IEEE Global Communications Theory Symposium (GLOBECOM), St. Louis, MO, Nov 28-Dec 2, 2005 (accepted and to appear).
L. Yang, C. Wakayama, and C.-J. R. Shi, "Top-down design of A pi/4 DQPSK transceiver with noise and nonlinearity aware behavioral modeling",
IFIP VLSI-Systems-on-Chip Conference, Perth, Australia, Oct. 17-19, 2005 (accepted and to appear).
E. Normark, L. Yang, C. Wakayama, P.V. Nikitin, and C.-J. R. Shi, "VHDL-AMS modeling and simulation of a Pi/4 DQPSK transceiver system", pp. 119-124 in
Proc. IEEE Behavioral Modeling and Simulation Conf. (BMAS'04), San Jose, CA, Oct. 2004.
P. V. Nikitin, E. Normark, C. Wakayama, and C.-J. R. Shi, "VHDL-AMS modeling and simulation of a BPSK transceiver system",
Proc. of IEEE International Conf. on Circuits and Systems for Communications, Moscow, Russia, June 2004.