Any suggestions for improvements to the models will be most welcome. Minor support for the models will be provided as quickly as possible. Major support and translation services can be available for a fee. These models represent student-developed software and may need some support, particularly for the more recently developed models. All the models are currently written in Saber MAST HDL but they can be easily translated into the IEEE Standard HDL, VHDL-AMS, to enable them to run on a wider variety of simulators. Translation is expected to require approximately 12 hours for each page of MAST code translated. Translation into Verilog-A or Verilog-AMS is discouraged because of the difficulties described in the following two paragraphs.

VHDL-AMS is the analog and mixed signal extension to the existing VHDL digital HDL approved in 1999. An analog only extension to the existing Verilog digital HDL was released as Verilog-A in 1997. A mixed signal version Verilog-AMS is under development and will eventually become a second IEEE standard analog HDL.

The main difference between these two HDLs is that VHDL-AMS is capable of automatically converting transient models (constructed of non-linear differential equations) into small-signal ac models while Verilog-A or Verilog-AMS requires separately designed and implemented small-signal ac models to provide better compatibility with SPICE-based simulators. For simple models, this separate implementation of small-signal ac models is easily accomplished. However for complex models, the implementation of separate ac models becomes very difficult. Such ac models are particularly difficult to design for power bipolar models where the internal operating state depends upon the presence of charge injected at previous times. Thus, VHDL-AMS is strongly preferred over Verilog-A/MS, particularly for compact models of power semiconductor devices.