The increasingly common deep-submicron technology (< 0.5 um) has resulted in stringent conditions under which designs are performed. The attributes of the deep sub-micron design environment include increasing circuit functionality and operating frequency, reduced power supply voltage, reduced or bounded die size, increasing process variability, and skyrocketing fabrication costs.
Our current research in VLSI modeling and simulation focus on three important problem areas that are of great concern to the deep sub-micron IC design community:
1) VLSI timing simulation with analog modeling emphasis,
2) parasitic RC reduction for post-layout verification, and
3) substrate and power-supply switching noise modeling and simulation.
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Sponsors: National Science Foundation National Young Investigator (1992-1997)
Abstract: The increasingly common deep-submicron technology (< 0.5 um) has resulted in stringent conditions under which designs are performed and verified. Effects that were previously disregarded are becoming important. For example, reduced power supply voltage and higher operating frequency lead to more noise and signal integrity problems and devices that appear more analog. Traditionally, SPICE is ideal to simulate deep-submicron circuit design since it closely mimics the detailed physical circuit behavior. However it is only practical for small to medium-scale problems. Our research emphasizes transistor-level timing simulator with analog emphasis. The goal is to provide a new simulation approach with SPICE-like accuracy and logic- or switch-level performance.
Our research has led to the development of ADM, a timing simulation based on closed-form solution. ADM, a commercially available simulation tool, is now used by more than 40 companies worldwide for the design of processor, memory and mixed-signal ICs.
Significant publications:
Y. H.Chang, A.T. Yang, "Analytic Macromodeling and Simulation of Strongly-Coupled Mixed Analog-Digital Integrated Circuits," Proceeding of IEEE 1992 Internation Conference on Computer-Aided Design, Nov. 1992, pp. 244-247.
A.T. Yang, Y. H.Chang., "Physical Timing Modeling for Bipolar VLSI," IEEE Journal of Solid-State Circuits, Vol. 27, No. 9, Sept. 1992, pp. 1245-1254.
A.T. Yang., Y. H.Chang., D. Saab, I.N. Hajj, "Switch-Level Timing Simulation of Digital Bipolar ECL Circuits," IEEE Transaction on Computer-Aided Design, Vol. 12, No. 4, April 1993, pp. 515-530.
J. Chen, A.T. Yang., "A Statistical Approach Based on Nonparametric Performance Macromodeling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 7, July 1995, pp. 794-802.
Sponsors: Cypress IC Design Center, National Semiconductor
Abstract: As monolithic mixed analog-digital ICs reach higher levels of integration, modeling and simulation, the impact of fast switching transients have become increasingly important. Two effects are primarily responsible for the deleterious "switching noise" phenomena observed in fabricated circuits. First, digital waveforms can disturb the performance of precision analog circuitry via crosstalk through the common chip substrate. A second important phenomenon involves interconnect parasitics and their impact on transient power bus voltage drops.
We have developed a new methodology for developing simulation, synthesis, and verification models to analyze the globalelectrical behavior of the non-ideal semiconductor substrate. A triangular discretization method is employed to generate RC equivalent-circuit substrate models which are far less complex than those formulated by conventional techniques. The methodology has been implemented in SNAPPLE (Switching Noise Analysis Package based on Post-Layout Extraction). This CAD package is the first substrate analysis package available to date. SNAPPLE is currently being utilized for substrate noise simulation of advanced mixed-signal designs (PLLs, and data converters) at Cypress IC Design Center and National Semiconductor.
Significant Publications:
I.L. Wemple, A.T. Yang, "Mixed-Signal Switching Noise Analysis using Voronoi-Tessellated Substrated Macromodels," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 12, Dec. 1995, pp. 1459-1469.
K. Kerns, I.L. Wemple, A. T Yang, "Efficient Substrate Noise Analysis for Monolithic Mixed-Signal ICs," Special Issue on Modeling and Simulation of Mixed Analog-Digital Systems, International Journal on Analog Integrated Circuits and Signal Processing, in press, 1996.
Sponsors: Catalyst Foundation, Tektronix Corp.
Abstract: The trends in industry are to design CMOS VLSI circuits with small devices, higher clock speeds, lower power consumption, and these increase the importance of modeling layout-dependent parasitics for signal integrity analysis. Very often, the layout-dependent effects are modeled solely with lumped resistors and capacitors which form linear, multiport networks. However, the networks are typically so large that simulation becomes impractical or impossible given the time and memory constraints.
Recently, we proposed a new network reduction formulation, referred to as Pole Analysis via Congruence Transformation (PACT). Unlike previous techniques proposed, PACT guarantees "absolute stability" of the reduced network. In addition, PACT guarantees "accuracy of fit" up to a user-specified frequency of operation. These are keys to the practical application of the research to realistic industry problems. A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT has been developed.
Significant Publications
S.Corey, A.T. Yang, "Interconnect Characterization Using Time Domain Reflectometry," IEEE Transactions on Microwave Theory and Techniques, Vol. 43, No. 9, Sept. 1995, pp. 2151-2156.
K. Kerns, A.T. Yang, "Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms," 1995 Proceeding of IEEE International Conference on Computer-Aided Design, Nov. 1995, pp. 207-214.
Sponsors: National Science Foundation, Nineteen Industrial Firms and the
Washington Technology Center.
Abstract: NSF CDADIC is an industry-university research consortiumthat is part of the National Science Foundation IUCRC (Industry-University Cooperative Research Center) program. University participants include: Washington State University, the University of Washington, Oregon State University, and the State University of New York at Stony Brook. CDADIC's mission is to advance the state-of-the-art for design tools, testing techniques, and circuit design methodologies for analog and analog-digital integrated circuits.
Sponsor: National Science Foundation
Abstract: This research program addresses the problem of fault modeling and test generation for mixed-signal integrated circuits. Defect statistics will be used to derive comprehensive fault models, which will include functional faults usable in design for test and test generation. New test generation algorithms will be derived, and techniques will be developed to interface the analog tests with the digital circuitry in a mixed-signal circuit.
Sponsor: Washington Technology Center
Abstract: The Microelectronics Group provides design and test support to the electronics and instrument industry in the Pacific Northwest. It incorporates aspects of the Microsensor Laboratory, the Compound Semiconductor Laboratory, and CDADIC (the NSF industry-university Center for Design of Analog and Digital ICs).
Sponsor: Washington Technology Center
Abstract: The goal of this project is to develop an electronic device that will both measure and enhance the compliance of young orthodontic patients wearing a common removable orthodontic appliance. The miniaturized device uses a low-energy consumption, battery-powered microprocessor and sensors to assess use of the orthodontic appliance. In addition, psychological principles have been incorporated into our design such that this model, as opposed to previous attempts by other investigators, may dramatically improve compliance and consequently treatment outcomes.
Sponsor: Semiconductor Research Corporation
Abstract: This research seeks to build a cohesive built-in self-test (BIST) system for analog and mixed-signal integrated circuits designed in CMOS, bipolar, or the combined BiCMOS technologies.
The focus of the project includes: (1) design-for-test techniques for continuous-time, switched-capacitor, switched-current circuits, (2) signature analysis techniques, and (3) integration of IEEE Standard 1149.1 and P1149.4 (Mixed-Signal Test Bus Standards) to support both on-chip and off-chip BIST strategies.
Sponsor: Boeing Defense & Space Group
Abstract: This research includes control and acquisition integrated circuit (IC) development which develops an IC with multiplexing and digital/analog boundary and internal scan facilities to be placed at strategic locations in MCM. Develop and characterize new forms of analog scan such as current-based sample and hold. It also includes built-in test IC development which is developing building blocks that can be pasted together to develop custom stimulus and measurement capability on MCM. It also addresses accessibility analysis and scan insertion along with test vehicle design, prototyping and failure analysis.
Sponsor: The Boeing Company
Abstract: Antennas in an array configuration are often strongly coupled and should be modeled as a multiport load impedance to the transceiver electronics. By varying the coupling network between the transceiver and the antenna, various system performance criteria can be greatly effected. Examples of specified performance criteria that depend on the coupling network include the transmit pattern, the received signal to noise ratio, and the system bandwidth.
The research is directed towards the development of design procedures for the creation of coupling networks that allow broad band power delivery to multiport loads, such as array antennas. The research can also be described as "Broad Band Matching" extended to lossless multiport coupling networks, a challenging unsolved problem at this time.
Sponsor: National Science Foundation, Center for Design of Analog-Digital Integrated Circuits
Abstract: Dozens of new power semiconductor device models have been produced by this power semiconductor device modeling project in the last seven years. Many of these device models are now available in the commercial circuit simulators used in power electronics.
Models have been developed for power P-i-N diodes, step-recovery-diodes, vertical power MOSFETs, lateral power MOSFETs, BJTs, diacs, SCRs, and GTOs. Generally, several different levels of models have been designed for each device type to provide different speed-accuracy tradeoffs. Considerable effort has been devoted to model validation, the process of defining performance standards for device models in common simulation applications.
The lumped-charge modeling methodology was developed at the University of Washington specifically for the modeling of devices like power semiconductors where internal charge storage is a significant factor in performance. This approach produces physically-based dynamic models with superior simulation speed and accuracy. Dynamic temperature effects can also be easily included. The models are also sufficiently simple to enable direct parameter extraction, a feature provided by few other circuit simulator models. The method is now being used by several other model designers.
Future modeling efforts are to focus on the special power devices used in power integrated circuits. New modeling methodologies are being investigated to enable stress testing and failure studies to be performed on circuit simulators. Also planned are the design of degradation models for simulation of device degradation under electrical or thermal stress.
Significant publications and presentations include:
I. Budihardjo, P. O. Lauritzen and H.A. Mantooth, "Performance Requirements for Power MOSFET Models," IEEE Transactions on Power Electronics, (in press).
I. Budihardjo, P.O. Lauritzen, K.Y. Wong, R.B. Darling and H.A. Mantooth, "Defining Standard Performance Levels for Power Semiconductor Devices," IAS Annual Meeting Proceedings, Oct. 1995.
C. L. Ma and P.O. Lauritzen, "A Physics-Based GTO Model for Circuit Simulation," IEEE PESC Proceedings, Atlanta, GA, June 1995.
I. Budihardjo and P. O. Lauritzen, "The Lumped-Charge Power MOSFET Model, Including Parameter Extraction," IEEE Transactions on Power Electronics, May 1995.
C. L. Ma, P. O. Lauritzen, Pao-Yi Lin, I. Budihardjo and J. Sigg, "A Systematic Approach to Modeling of Power Semiconductor Devices Based on Charge Control Principles," IEEE PESC Power Electronics Specialists Conference, Taipei, Taiwan, June 1994.
C. L. Ma and P.O. Lauritzen, "A Simple Power Diode Model with Forward and Reverse Recovery," IEEE Transactions on Power Electronics, Oct. 1993.
Sponsor: Semiconductor Research Corporation, Intel Corporation, Digital Equipment Corporation, LSI Logic, Cadence DesignSystems
Abstract: A key problem faced by chip and system designers today is getting a handle on the floorplan and timing of a design well before the intended fabrication technology has been nailed down. Since such an early floorplanning process is not available today, chips are often designed inefficiently. This leads to initial designs, well down stream, which are much too large to fit on the intended package, leading to panicky redesigns. Or, a lot of unused space is left on the chip, which increases fabrication costs. And many times the intended cycle times are deemed nearly impossible, again well down stream, leading to costly redesigns at a point when the product should have been shipping. Our research plan has a very focussed theme, namely, the early floorplanning problem. There are three tasks to accomplish early floorplanning, namely, circuit implementation, cell library generation and chip-level layout:.
1) One must be able to implement all the circuitry that may be on a chip. Some circuitry will always be done using static CMOS while other more delay critical circuitry will be implemented in high speed technologies such as domino logic.
2) A method for generating the necessary cell libraries must be available. For truly early floorplanning, the fabrication process isn't ready yet and therefore the manual process of generating the cell libraries for various technologies hasn't begun. All we need is a rough idea as to the design rules and we can generate all the necessary cells. It is a simple matter to update the design rules and automatically regenerate the cells at any later date.
3) There must be some mechanism for chip-level layout, namely, timing driven placement and routing. The user of our software may or may not elect to actually use our block layouts for their actual design. In any event, areas, parasitics and delays will be well estimated since they are based on actual functional layouts.
Significant publications and presentations include:
L. Liu and C. Sechen, "A Multi-Layer Chip-Level Global Router," Proc. of the Fifth ACM/SIGDA Physical Design Workshop, Reston, Virginia, April 15-17, 1996
L. Liu and C. Sechen, "Multi-Layer Pin Assignment for Macro Cell Circuits," Proc. of the Fifth ACM/SIGDA Physical Design Workshop, Reston, Virginia, April 15-17, 1996.
G. Yee and C. Sechen, "Clock-Delayed Domino for Adder and Combinatorial Logic Design," Proc. of the Fifth ACM/SIGDA Physical Design Workshop, Reston, Virginia, April 15-17, 1996
B. Guan and C. Sechen, "Efficient Standard Cell Generation When Diffusion Strapping is Required," Proc. of the Fifth ACM/SIGDA Physical Design Workshop, Reston, Virginia, April 15-17, 1996.
H. P. Tseng and C. Sechen, "A Gridless Multi-Layer Channel Router Based on a Combined Constraint Graph and Tile Expansion Approach," Proc. of the Fifth ACM/SIGDA Physical Design Workshop, Reston, Virginia, April 15-17, 1996.
W. Swartz and C. Sechen, "Timing Driven Placement for Large Circuits," Proc. 1995 Design Automation Conference (DAC), San Francisco, CA, June 1995.
W. Sun and C. Sechen, "A Loosely Coupled Parallel Algorithm for Standard Cell Placement," IEEE Int. Conf. on Computer-Aided Design (ICCAD), Nov. 6-10, 1994, Santa Clara, CA, pp. 137-144.
W. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits," IEEE Transactions on Computer-Aided Design, Vol. 14, No. 3, March 1995, pp. 349-359