Thesis
1. Alicia Manthe, Ph.D., June 2003
2. Bo Wan, Ph.D., June 2004
3. Roy Hartono, Master, May 2004

Journal Papers

1. N. Jangkrajarng, S. Bhattacharya, R. Hartono, and R. Shi, "IPRAIL - Intellectual Property Reuse-based Analog IC Layout Automation", accepted for a special issue of "Integration, the VLSI journal" published by Elsevier science
2. G. Shi and C.-J. Richard Shi, "Model order reduction by dominant subspace projection: error bound, subspace computation and circuit application," IEEE Trans. Circuits and Systems (Part I: Regular Papers), 2004 (in press).

Conference Papers
1. B. Hu, G. Shi, and R. Shi, "Symbolic model order reduction", IEEE BMAS Conference, Oct. 2003, San Jose, CA

2. P. Nikitin, E. Normark, and R. Shi, "Distributed electrothermal modeling in VHDL-AMS", IEEE BMAS conference, Oct. 2003, San Jose, CA

3. P. Nikitin, W. Yam, and R. Shi, "Parametric equivalent circuit extraction for VLSI structures", IFIP International VLSI-SoC Conference, Dec. 2003, Darmstadt, Germany

4. Z. Li and R. Shi, "SILCA: Fast-yet-accurate time-domain simulation of VLSI circuits with strong parasitic coupling effects", IEEE/ACM International Conference on Computer-Aided Design, Nov. 2003, San Jose, CA

5. L. Yang and R. Shi, Frosty: a fast hierarchy extractor for industrial CMOS circuits", IEEE/ACM International Conference on Computer-Aided Design, Nov. 2003, San Jose, CA

6. L. Zhou, B. Hu, B. Wan and R. Shi, Rapid BSIM model implementation with VHDL-AMS/Verliog-AMS and MCAST Compact Model Compiler", IEEE SoC Conference, Sept. 2003, Portland, OR

7. P. Nikitin, C.-J. R. Shi, and B. Wan, "Modeling partial differential equations in VHDL-AMS", IEEE SoC Conference, Sept. 2003, Portland, OR

8. B. Wan, B. Hu, L. Zhou and R. Shi, "MCAST: An abstract-syntax-tree based model compiler for circuit simulation", IEEE Custom Integrated Circuits Conference, Sept 2003, San Jose, CA

9. N. Jangkrajarng, S. Bhattacharya, R. Hartono, and R. Shi, "Automatic analog layout retargeting for new processes and device sizes", ISCAS, May 2003, Bangkok, Thailand

10. S. Bhattacharya and R. Shi, "Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis", ISCAS, May 2003, Bangkok, Thailand

11. G. Shi and C.-J. Richard Shi, "Parametric reduced order modeling for interconnect analysis," in Proc. Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2004, pp. 774 - 779.

Thesis
1. Optimum Logic Encoding and Layout Wiring for VLSI Design: A Graph-Theoretic Approach, Ph.D. Disseration, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, December 1993
Thesis supervisor: J. A. Brzozowski
External Examiner: E. S. Kuh, UC Berkeley

Book Chapters
1. C.-J. Shi, Fault Simulation, Chapter 3 and pp. 55-92 in Analog and Mixed-Signal Test, Bapiraju Vinnakota (ed.), Prentice-Hall, 1998.
2. C.-J. Shi and W. Tian, Simulation and Sensitivity of Linear(ized) Analog Circuits under Parameter Variations, Chapter 44 and pp. 540-551 in VLSI: Integrated Systems on Silicon, Ricardo Reis and Luc Claesen (eds.), Chapman & Hall, 1997.
3. C.-J. Shi and A. Vachoux, VHDL-AMS Design Objectives and Rationale, Chapter 1 and pp. 1-30 in Modeling in Analog Design, vol. 2 in Series Current Issues in Electronic Modeling (CIEM), Jean-Michel Berge, Oz Levia and Jacques Rouillard (eds.), Kluwer Academic Publishers, 1995.

Journal Papers
1 . C.-J. Shi and X.-D. Tan, ``Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, July 2001.
2 . C.-J. Shi and W. Tian, ``Efficient fault simulation and test generation for linear analog circuits under parameter variations", IEEE Trans. Computer-Aided Design.
3 . C.-J. Shi and X.-D. Tan, ``Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear.
4 . T. Pi and C.-J. Shi, ``Testability analysis of analog circuits via determinant decision diagrams", IEICE Transactions, vol. E83-A, no. 12, pp. 2608-2613, Dec. 2000.
5. M. W. Tian and C.-J. Shi, ``Worst-case tolerance analysis of linear analog circuits using sensitivity bands", IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 47, no. 8, pp. 1138-1145, August 2000.
6 . X.-D. Tan and C.-J. Shi, ``Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams", IEEE Trans. Computer-Aided Design, vol. 19, no. 4, pp. 401-412, April 2000.
7. C.-J. Shi and X.-D. Tan, ``Canonical symbolic analysis of large analog circuits with determinant decision diagrams", IEEE Trans. Computer-Aided Design, vol. 19, no. 1, pp. 1-18, Jan. 2000.
8. C.-J. Shi and W. H. Kao, ``Guest editorial---special issue on behavioral modeling and simulaiton of mixed-signal/mixed-technology systems", IEEE Trans. Circuits and Systems --- II: Analog and Digital Signal Processing, vol. 46, no. 10, pp. 1261-1261, Oct. 1999.
9. C.-J. Shi and W. Tian, ``Simulation and sensitivity of linear analog circuits under parameter variations by robust interval analysis", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 4, no. 3, July 1999.
10. C.-J. Shi and J.A. Brzozowski, ``A characterization of signed hypergraphs and its applications to VLSI via minimization and logic synthesis", Discrete Applied Mathematics, vol. 89, no. 1-3, pp. 223-243, Dec. 1998.
11. C.-J. Shi, ``Entity overloading for mixed-signal abstraction in VHDL", Journal of Information Science and Engineering, vol. 14, no.3, pp. 633-644, September 1998.
12. N. Godambe and C.-J. Shi, ``Behavioral-level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS", Journal of Electronic Testing: Theory and Applications (JETTA), vol. 9, no. 3, August 1998.
13. C.-J. Shi and J.A. Brzozowski, ``Cluster-cover: A theoretical framework for a class of VLSI-CAD optimization problems", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 3, no. 1, pp. 76-107, Jan. 1998.
14. C.-J. Shi, A. Vannelli and J. Vlach, ``Performance-driven layer assignment by integer linear programming and path-constrained hypergraph partitioning", Journal of Heuristics, vol. 3, no. 3, pp. 225-243, November 1997.

Conference Papers
1. X.-D. Tan and C.-J. Richard Shi, ``Fast power-ground network optimization using equivalent circuit modeling", in Proc. 38th IEEE/ACM Design Automation Conference (DAC'2001), Las Vegas, NE, June 2001.
2. D. Lungeanu and C.-J Shi, ``Distributed and parallel VHDL simulation", accepted by Design, Automation and Test in Europe Conference (DATE'00), Paris, France, March 2000.
3. Y. Bourai and C.-J Shi, ``Layout compaction for yield optimization via critical-area minimization", accepted by Design, Automation and Test in Europe Conference (DATE'00), Paris, France, March 2000.
4. T. Pi and C.-J. Shi, ``Analog testability analysis by determinant-decision diagrams-based symbolic analysis", accepted by Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 2000.
5. X. Tan and C.-J. Shi, ``Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams," accepted by Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 2000.
6. D. Lungeanu and C.-J Shi, ``Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization", accepted by IEEE/ACM International Conference on Computer-Aided Design (ICCAD'99), San Jose, CA, Nov. 1999. (106 out of 317 submissions were selected)
7. X. Tan, C.-J. Shi, D. Lungeanu, J.-C. Lee and L.-P. Yuan, ``Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings", pp. in IEEE/ACM 36th Design Automation Conference (DAC'99), New Orleans, LA, June 21-25, 1999. (Best Paper Award.)
8. X. Tan and C.-J. Shi, ``Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams", pp. 448-453 in Proc. Design, Automation and Test in Europe (DATE'99), Munich, Germany, Mar. 10-13, 1999.
9. Y. Bourai and C.-J. Shi, ``Symmetry detection for analog layout recycling", pp. 5-7 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 18-21, 1999.
10. X. Tan and C.-J. Shi, ``Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis", pp. 1-4 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 18-21, 1999.
11. C.-J. Shi and W. Tian, ``Automatic test generation for linear(ized) analog circuits under parameter variations", pp. 501-506 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'98), Tokyo, Japan, Feb. 10-13, 1998. (Nominated by the program committee for the Best Paper Award.)
12. W. Tian and C.-J. Shi, ``Efficient DC fault simulation of nonlinear analog circuits", pp. 899-904 in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE'98), Paris, France, Feb. 23-26, 1998. (merged EuroDAC and ED&TC conferences.) ( 122 out of 448 submissions were selected)
13. X. Tan and C.-J. Shi, ``Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams", pp. 318-321 in Proc. IEEE International Symposium on Circuits and Systems, vol. VI, 1998.
14. W. Tian and C.-J. Shi, ``Worst-case analysis of linear analog circuits using sensitivity bands", pp. 110-113 in Proc. IEEE International Symposium on Circuits and Systems, vol. VI, 1998.
15. W. Tian and C.-J. Shi, ``Nonlinear Analog DC Fault Simulation by One-Step Relaxation", pp. 126-131 in Proc. 16th IEEE VLSI Test Symposium, Hyatt Regency Monterey, Monterey, CA, April 26-30, 1998. (Best Paper Award.)
16. C.-J. Shi and X. Tan, ``Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits", pp. 463-466 in Proc. IEEE Custom Integrated Circuits Conference, San Diego, CA, May 12-14, 1998.
17. C.-J. Shi, ``Block-level fault isolation using partition theory and logic minimization techniques", pp. 319-324 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'97), Chiba, Japan, Jan. 28-31, 1997.
18. C.-J. Shi, ``Solving constrained via minimization by compact linear programming", pp. 635-640 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'97), Chiba, Japan, Jan. 28-31, 1997.
19. N. Godambe and C.-J. Shi, ``Behavioral-level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS", pp. 177--183 in Proc. IEEE VLSI Test Symp. (VTS'97), Monterey, CA, April 27 - 30, 1997 (62 out of 178 submissions were accepted).
20. W. Tian and C.-J. Shi, ``Rapid frequency-domain analog fault simulation under parameter tolerances", pp. 275 -- 280 in Proc. IEEE/ACM Design Automation Conference (DAC'97), Anaheim, CA, June 9-13, 1997 (139 out of 389 submissions accepted).
21. C.-J. Shi and W. Tian, ``Simulation and sensitivitity of linear(ized) analog circuits under parameter variations", in Proc. 9th IFIP International Conference on Very Large Scale Integration (VLSI'97), Gramado, BRAZIL, August 26-29, 1997.
22. C.-J. Shi, ``Block-level fault isolation for mixed-signal multichip modules under parameter varations", IEEE/IMAPS MCM Test IV Workshop, Napa Valley, California, Sept. 14 - 17, 1997.
23. C.-J. Shi, Y. Ye and X. Tan, ``Behavioral model optimization via sensitivity-enhanced genetic search", pp. 17-24 in Proc. IEEE/VIUF International Workshop on Behavioral Modeling and Simulation, Washington DC, Oct. 1997.
24. C.-J. Shi and X. Tan, ``Symbolic analysis of large analog circuits with determinant decision diagrams", pp. 366-373 in Proc. IEEE/ACM International Conference on Computer-Aided Design, (ICCAD'97), San Jose, CA, November 9-13, 1997. ( 102 out of 341 submissions were accepted.)
25. C.-J. Shi, ``Inclusive-OR Boolean satisfiability for via minimization and constrained encoding in VLSI design", Invited Paper in DIMACS Workshop on Satisfiability Problem: Theory and Applications, March 11-13, 1996.
26. O. Coudert and C.-J. Shi, ``Exact multi-layer topological planar routing", pp. 179-182 in Proc. IEEE Custom Integrated Circuit Conference (CICC'96), San Diego, CA, May 5-8, 1996.
27. C.-J. Shi, ``Finding a minimal test set for analog fault diagnostic dictionary", pp. 303-308 in Proc. International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability, Beijing, China, July 2-3, 1996.
28. C.-J. Shi, ``Fault isolation for mixed-signal multichip modules", in IEEE MCM Test II Workshop, Napa Valley, California, Sept. 15 - 18, 1996.
29. C.-J. Shi, ``Entity overloading for mixed-signal abstraction in VHDL", pp. 562-567 in Proc. European Design Automation Conference (EuroDAC/EuroVHDL'96), Geneva, Switzerland, September 16-20, 1996. (Nominated by the program committee for the Best Paper Award.)
30. C.-J. Shi and N. Godambe, ``Behavioral fault modeling and simulation of phase-locked loops using a VHDL-A like language", pp. 245-250 in Proc. IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester, N.Y., September 23-27, 1996. (Acceptance Ratio: 0.5)
31. C.-J. Shi, A. Vannelli and J. Vlach, ``Performance-driven layer assignment for printed circuit boards and integrated circuits", pp. 171-174 in Proc. IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester, N.Y., September 23-27, 1996. (Acceptance Ratio: 0.5)
32. O. Coudert and C.-J. Shi, ``Exact dichotomy-based constrained encoding", pp. 426-431 in Proc. IEEE International Conference on Computer Design (ICCD'96), Austin, Texas, October 7-9, 1996.
33. C.-J. Shi and J. A. Brzozowski, ``A framework for the analysis and design of algorithms for a class of VLSI optimization problems", pp. 67-74 in Asia and South Pacific Design Automation Conference (ASP-DAC'95), Aug. 29 - Sept. 1, 1995. (Nominated by the program committee for the Best Paper Award.)