SSRL Publications
2008 
2007 
2006 
2005 
2004 
2003 
2002 
2001 
2000 
1999 
1998 
1997 
1996 
Pre 1996
Notes: (1)Publications by IEEE, ACM, and Kluwer are copyrighted
by the respective organizations.
Reproduction of any material contained in these publications requires
explicit permission by the publisher.
(2) Conference papers marked by * appeared later
as extended versions in journals.
2008:

L. Zhang, N. Jangkrajarng, S. Bhattacharya, and C.J. R. Shi,
"Parasiticaware optimization and retargeting of analog layouts:
a symbolic template approach",
IEEE Trans. on ComputerAided Design,
2008, to appear.

B. Hu and C.J. R. Shi, "Simulation of closelyrelated
dynamic nonlinear systems with application
to processvoltagetemperature corner analysis",
IEEE Trans. on ComputerAided Design,
2008, to appear.

L. Zhang, Y. Jiang, and C.J. R. Shi, "Symmetryaware placement with transitive closure graphs for analog layout design",
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'08)
, Japan, Jan 2008.
2007:

L. Zhou, C. Wakayama, R. Panda, N. Jangkrajarng, B. Hu, and C.J. R. Shi, "Implementing a 2Gbs 1024bit ½rate lowdensity parity check code decoder in threedimensional integrated circuits", invited paper,
in
Proc. IEEE International Conf. on Computer Design
, Lake Tahoe, CA, Oct. 2007.
 M. Su, L. Zhou and C.J. R. Shi, "Maximizing the throughputarea efficiency of fullyparallel lowdensity paritycheck decoding with Cslow retiming and asynchronous deep pipelining", in
Proc. IEEE International Conf. on Computer Design
, Lake Tahoe, CA, Oct. 2007.
 W. Chen, G. Shi and C.J. R. Shi, "A graphreduction approach to symbolic circuit analysis",
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'07)
, Japan, Jan 2007

L. Zhou, C. Wakayama, and C.J. R. Shi, "CASCADE: A standard supercell design methodology with congestiondriven placement for threedimensional interconnectheavy very large scale integrated circuits",
IEEE Trans. on ComputerAided Design,
vol. 26, no. 7, July 2007.

P. Nikitin, and C.J. R. Shi,
"VHDLAMS based modeling and simulation of mixedtechnology
microsystems: A tutorial",
Integration, the VLSI Journal,
vol. 40, no. 3, pp. 261273, April 2007.
2006:

Z. Li and C.J. R. Shi, "A quasiNewton preconditioned NewtonKrylov method
for robust and efficient timedomain simulation of
integrated circuits with strong parasitic couplings",
IEEE Trans. on ComputerAided Design, Dec. 2006.

L. Zhang, and C.J. Shi,
"Templatebased parasiticaware optimization and retargeting
of analog and RF integrated circuit layouts ",
IEEE/ACM International Conf. on ComputerAided design,
San Jose, Nov 2006.

B. Hu and C.J. Shi, "Model compiler driven simulation of
multitechnology systems ",
Proc. IEEE Symp. Circuits and Systems (ISCAS),
May 2006.

C.J. R. Shi, M. Tian and G. Shi,
"Nonlinear DC fault simulation:
onestep relaxation and adaptive simulation continuation",
IEEE Trans. on ComputerAided Design,
vol. 25, no. 7, pp. 13921400, July 2006.

G. Shi, B. Hu, and C.J. R. Shi,
"On symbolic model order reduction",
IEEE Trans. on ComputerAided Design,
vol. 25, no. 7, pp. 12571272, July 2006.

Z. Li and C.J. R. Shi,
"SILCA: SPICEaccurate
iterative linearcentric analysis for efficient
timedomain simulation of VLSI circuits
with strong parasitic couplings",
IEEE Trans. on ComputerAided Design,
vol. 25, no. 6, pp. 10871103, June 2006.

S. Bhattacharya, N. Jangkrajarng, and C.J. R. Shi,
"Multilevel symmetry constraint generation for retargeting large analog layouts" ,
IEEE Trans. on ComputerAided Design,
vol. 25, no. 5, pp. 945960, June 2006.

L. Yang, H. Liu, and C.J. R. Shi,
"Construction and FPGA implementation of lowerrorfloor multirate lowdensity paritycheck code decoders",
IEEE Trans. on Circuits and SystemsI,
vol. 53, no. 4, pp. 892904, April 2006.

*Z. Li and C.J. R. Shi, "Robust and efficient timedomain circuit simulation by quasiNewton preconditioned NewtonKrylov iterative methods",
Proc. Asia and SouthPacific Design Automation Conf. (ASPDAC'06),
Japan, Jan 2006 (135 out of 432 papers were accepted).

Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, and C.J. Richard Shi, "A highthroughput lowPower fully parallel 1024bit
1/2 rate low density parity check code decoder in 3dimensional integrated circuits",
Proc. Asia and SouthPacific Design Automation Conf. (ASPDAC'06),
Japan, Jan 2006.
2005:

L. Yang and CJ. R. Shi, "FROSTY: A program for fast extraction of highlevel structural representation from circuit description for industrial CMOS circuits," Integration, the VLSI Journal, vol. 39, no. 2, Dec. 2005.
(Science Direct: Top 25 hottest article in the journal).

B. Hu, C. Wakatama, L. Zhou and C.J. R. Shi,
"Rapid implementation of semiconductor
device models in SPICE with
MCAST compact model compiler",
IEEE Circuits and Devices, vol. 21, no. 4,
July 2005.

G. Shi and C.J. R. Shi,
"Model order reduction by dominant subspace projection: error bounds, subspace approximation and circuit applications,"
IEEE Trans. on Circuits and SystemsI: Regular Papers, vol. 52, no. 5,
pp. 975993, May 2005.

B. Wan and C.J. R. Shi, "Hierarchical multidimensional table lookup for modelcompilerbased circuit simulation,"
IEE Proceedings on Computers and Digital Techniques,
vol. 152, no. 1, pp. 3944, Jan. 2005.

*L. Yang, H. Liu and C.J. R. Shi, "VLSI implementation of lowerrorfloor and capacityapproaching performance lowdensity paritycheck codes with multirate capacity",
IEEE Global Communications Theory Symposium (GLOBECOM),
St. Louis, MO, Nov 28Dec 2, 2005.

B. Hu and C.J. R. Shi, "Fastyetaccurate processvoltagetemperature (PVT) simulation by combined direct and iterative methods",
IEEE/ACM International Conf. on ComputerAided Design, Nov. 2005 (acceptance rate: 0.25)

L. Yang, C. Wakayama, and C.J. R. Shi, "Topdown design of A pi/4 DQPSK transceiver with noise and nonlinearity aware behavioral modeling",
IFIP VLSISystemsonChip Conference,
Perth, Australia, Oct. 1719, 2005.

V. Jandhyala, Y. Kuga, D. Allstot, and C.J. R. Shi, "Bridging circuits and electromagnetics in a curriculum aimed at microelectronic analog and microwave simulation and design",
IEEE Frontier in Education Conf., 2005.

*L. Yang, H. Liu and C.J. R. Shi, "A cycle elimination method for constructing VLSIoriented LDPC codes",
IEEE 62nd Vehicle Technology Conf., Dallas, TX, USA, September 25 to 28, 2005.(625 out of 1084 accepted).

S. Bhattacharya, N. Jangkrajarng, and C.J. R. Shi, "Templatedriven parasiticaware optimization of analog integrated circuit layouts",
IEEE/ACM Design Automation Conf., June 2005 (154 out of 735 accepted).

B. Hu, Z. Li, L. Zhou, C.J. R. Shi, K.H. Baek, and M.J. Choe, "Modelcompiler based efficient statistical circuit analysis: An industry case study of a 4GHz/6bit ADC/DAC/DEMUX ASIC",
Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'05), Kobe, Japan, May 2005.

L. Yang, C. Wakayama, and C.J. R. Shi, "Noiseaware behavioral modeling of a fractionalN frequency synthesizer",
Proc. Great Lake Symp. on VLSI, April 2005.

Z. Li and C.J. R. Shi, "An efficiently preconditioned GMRES method for fast parasiticsensitive deepsubmicron VLSI circuit simulation", in
Proc. Design Automation & Test in Europe Conf. (DATE'05), Munich, Germany, March 2005 (Nominated by the Technical Program Committee for Best Paper Award).

*L. Yang, M. Shen, H. Liu and C.J. R. Shi, ``An FPGA implementation of lowdensity paritycheck code decoder with multirate capability", pp. 760763 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'05), Shanghai, China, Jan. 2005 (177 out of 692 accepted).

R. Hartono, N. Jangkrajarng, S. Bhattacharya, and C.J. R. Shi, "Automatic device layout generation for analog layout retargeting", pp. 457462 in
Proc. International Conf. on VLSI Design, Jan. 2005.
2004:

Z. Li, R. Suravarapu, K. Mayaram and C.J. R. Shi, "Automatic extraction of layoutdependent substrate effects for RF MOSFET modeling,"
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87A, no. 12, pp. 33093317, Dec. 2004.

Y. Wang, D. Gope, V. Jandhyala, and C.J. R. Shi, "Generalized Kirchoff's current and voltage law formulation for coupled circuitelectromagnetic simulation with surface integral equations,"
IEEE Trans. on Microwave Theory and Techniques,
vol. 52, no. 7, pp. 16731682, July 2004.
Top download IEEEMTT paper in 2004 based on IEEE Explorer Statistics

X.D. Tan and C.J. R. Shi, "Efficient approximation of symbolic expressions for analog behavioral modeling and analysis,"
IEEE Trans. on ComputerAided Design, vol. 23, no. 6, pp. 907918, June 2004.

S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C.J. R. Shi, "Challenges and techniques for layout automation of radiofrequency integrated circuits", in
Proc. Asia Pacific Microwave Conf. (APMC'04), Dec. 2004.

E. Normark, L. Yang, C. Wakayama, P.V. Nikitin, and C.J. R. Shi, "VHDLAMS modeling and simulation of a Pi/4 DQPSK transceiver system", pp. 119124 in
Proc. IEEE Behavioral Modeling and Simulation Conf. (BMAS'04), San Jose, CA, Oct. 2004.

B. Wan, E. Acar, S. Nassif, and C.J. R. Shi, "Designadaptive device modeling in model compiler for efficient and accurate circuit simulation" pp. 400405 in
Proc. IEEE Behavioral Modeling and Simulation Conf. (BMAS'04), San Jose, CA, Oct. 2004.

B. Wan, P. V. Nikitin, and C.J. R. Shi, "Circuit level modeling and simulation of mixedtechnology systems", pp. 113116 in
Proc. IEEE SystemsonChip Conf (SoC'04)., Santa Clara, CA, Sept. 2004.

P. V. Nikitin, E. Normark, C. Wakayama, and C.J. R. Shi, "VHDLAMS modeling and simulation of a BPSK transceiver system",
Proc. of IEEE International Conf. on Circuits and Systems for Communications, Moscow, Russia, June 2004.

V. Jandhyala, P. Nikitin, J. D. Rockway, J. W. Rockway, N. Champagne, R. Sharpe. D. White, C.J. R. Shi, and D. Allstot, "Electromagnetic modeling and electromagnetic circuit cosimulation of mixedsignal systemsonchip", pp. 32813284 in Proc. IEEE APSURSI Symp., Monterey, CA, June 2004.

S. Bhattacharya, N. Jangkrajarng, R. Hartono, C.J. R. Shi, "Correctbyconstruction layoutcentric retargeting of large analog designs", pp. 139144 in
Proc. IEEE/ACM Design Automation Conf. (DAC'04), June 2004.

Z. Li and C.J. R. Shi, ``A coupled iterative/direct method for efficient timedomain simulation of nonlinear circuits with power/ground networks", pp. 165168 in
Proc. IEEE International Symp. on Circuits and Systems (ISCAS'04), Vancouver Canada, May 2004.

P. Nikitin, V. Jandhyala, D. White, N. Champagne, J. D. Rockway, C.J. R. Shi, C. Yang, G. Ouyang, Y. Wang, R. Sharpe and J. Rockway, "Modeling and simulation of circuitelectromagnetic effects in electronic design flow," pp. 244249 in
Proc. IEEE 5th International Symp. on Quality Electronic Design (ISQED'04), San Jose. CA, March 2004.

*B. Wan and C.J. R. Shi, "Hierarchical multidimensional table lookup for model compiler based circuit simulation," in
Proc. Design, Automation and Test in Europe Conf. (DATE'04), Paris, France, March 2004.

*G. Shi and C.J. R. Shi, "Parametric reduced ordering modeling for interconnect analysis," pp. 775780 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).

*Z. Li, R. Suravarapu, R. Hartono, S. Bhattacharya, K. Mayaram, and C.J. R. Shi, "CrtSmile: A CAD tool for CMOS RF transistor substrate modeling incorporating layout effects," pp. 163168 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).

*S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C.J. R. Shi, "Hierarchical extraction and verification of symmetry constraints for analog layout automation," pp. 400405 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04)
, Japan, Jan. 2004 (148 out of 291 accepted).

N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.J. R. Shi, "Multiple specifications radiofrequency integrated circuit design with automatic templatedriven layout retargeting," pp. 394399 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).
2003:

X.D. Tan and C.J. R. Shi, "Efficient DDDbased interpretable symbolic characterization of large analog circuits,"
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86A, no. 12, pp. 31193126, Dec. 2003.

X.D. Tan, C.J. R. Shi and J.C. Lee, "Reliabilityconstrained area optimization of VLSI power/ground networks via sequence of linear programmings,"
IEEE Trans. on ComputerAided Design,
vol. 22, no. 12, pp. 16781684, Dec. 2003.

N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.J. R. Shi, "IPRAIL: Intellectual property reuse based analog IC layout automation,"
Integration, the VLSI Journal,
vol. 36, no. 4, pp. 237262, Nov. 2003.

X.D. Tan and C.J. R. Shi, "Balanced multilevel multiway partitioning of analog integrated circuits for hierarchical symbolic analysis,"
Integration, the VLSI Journal, vol. 34, no.12, pp. 6586, May 2003.

X.D. Tan and C.J. R. Shi, "Efficient VLSI power/ground network sizing based on equivalent circuit modeling,"
IEEE Trans. on ComputerAided Design,
vol. 22, no. 3, pp. 277284, March 2003.

P. Nikitin, W. Lam, and C.J. R. Shi, "Parametric equivalent circuit extraction for VLSI structures," pp. 198203 in
Proc. IFIP VLSISoC Symp., Darmstadt, Germany, Dec. 2003 (46 out of 146 accepted as regular papers).

*L. Yang and CJ. R. Shi, "FROSTY: A fast hierarchy extractor for industrial CMOS circuits," pp. 741746 in
Proc. IEEE International Conf. on ComputerAided Design (ICCAD'03), Nov. 2003 (130 out of 490 accepted).

*Z. Li and C.J. R. Shi, "SILCA: Fastyetaccurate timedomain simulation of VLSI circuits with strong parasitic coupling effects," pp. 793799 in
Proc. IEEE International Conf. on ComputerAided Design (ICCAD'03), Nov. 2003 (130 out of 490 accepted).

*B. Hu, G. Shi and C.J. R. Shi, "Symbolic model order reduction," pp. 3440 in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS'03), San Jose, CA., Oct. 2003 (acceptance rate: 66%).

P. Nikitin, E. Normark, and C.J. R. Shi, "Coupled electricalthermal modeling in VHDLAMS," pp. 128133 in
Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS'03), San Jose, CA, Oct. 2003 (acceptance rate: 66%).

Y. Wang, D. Gope, V. Jandhyala, and C.J. R. Shi, "Integral equationbased coupled electromagnetic circuit simulation in the frequency domain," pp. 328331 in Proc IEEE International Conf. on Antennas and Propagation,
vol. 3, Sept. 2003 (same as C33).

B. Wan, B. Hu, L. Zhou and C.J. R. Shi, ``MCAST: An abstractsyntaxtree based model compiler for circuit simulation", pp. 249252 in
Proc. IEEE Custom Integrated Circuits Conf. (CICC'03),
San Jose, CA, Sept. 2003 (147 out of 380 papers were accepted).

P. Nikitin and C.J. R. Shi, "Modeling partial differential equations in VHDLAMS," pp. 345348 in
Proc. IEEE Application Scientific Integrated Circuits/SystemsonChip Conf. (SOC'03), Portland, Oregon, Sept. 2003.

L. Zhou, H. Bo, B. Wan, and C.J. R. Shi, ``Rapid BSIM model implementation with VHDLAMS/VerilogAMS and MCAST compact model compiler", pp. 285286 in
Proc. IEEE Application Scientific Integrated Circuits/SystemsonChip Conf. (SOC'03), Portland, Oregon, Sept. 2003.

Y. Wang, D. Gope, V. Jandhyala and C.J. R. Shi, "Integral equationbased coupled electromagneticcircuit simulation in the frequency domain,"
SRC TechCon Technical Digest, Dallas, August 2003 (Best Paper in Session Award, Mixed Signal Technology Session).

A. Manthe, Z. Li, and C.J. R. Shi, "Symbolic analysis of analog circuits with hard nonlinearity", pp. 542545 in
Proc. IEEE/ACM Design Automation Conf. (DAC'03), June 2003 (acceptance ratio: 25%).

*S. Bhattacharya and C.J. R. Shi, "Concurrent gate and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis," pp. 660663 in
Proc. IEEE International Symp. on Circuits and Systems (ISCAS'03), vol. 4, May 2003.

*N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.J. R. Shi, "Automatic analog layout resizing for process and performance retargeting," pp. 704707 in
Proc. IEEE International Symp. on Circuits and Systems (ISCAS'03), vol. 4, May 2003.

A. Manthe, Z. Li, C.J. R. Shi and K. Mayaram, "Symbolic analysis of nonlinear analog circuits," pp. 11081109 in
Proc. Design, Automation and Test in Europe Conf. (DATE'03), Munich, Germany, March 2003.

*X.D. Tan and C.J R. Shi, "Efficient DDDbased term generation algorithm for analog behavioral modeling," pp. 789794 in
Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'03), Japan, Jan. 2003.
2002:

V. Jandhyala, Y. Wang, D. Gope, and C.J. R. Shi, "A surfacebased integral equation formulation for coupled electromagnetic and circuit simulation,"
Microwave Optical Technology Letters,
vol. 34, no. 2, pp. 103106, July 2002.

D. J. Allstot, K. Choi, M. Mar, M. Rubeiz, C.J. R. Shi and R. Ward, "Parasiticaware synthesis of RF CMOS power amplifiers via simultaneous topology selection and device sizing," pp. 12421247 in
Proc. IEEE International Conf. on Communications, Circuits and Systems (ICCCAS'02), June 29July 2, 2002.

A. Manthe and C.J. R. Shi, "Finding minimal symbolic expressions for analog modeling", in Proc. IEEE International Conf. on Communications, Circuits and Systems (ICCCAS'02), June 29July, 2, 2002.

R. Suravarapu, K. Mayaram, and C.J. R. Shi, "A layout dependent and bias independent scalable substrate model for CMOS RF transistors," pp. 217220 in
Proc. IEEE Radio and Wireless Conf. (RAWCON'2002), Boston, MA, Aug. 2002.

*V. Jandhyala, Y. Wang, D. Gope and C.J. R. Shi, "Coupled electromagneticcircuit simulation of arbitrarilyshaped conducting structures using triangular meshes," pp. 3842 in
Proc. IEEE 3rd International Symp. on Quality Electronic Design (ISQED'02), March 2002, San Jose. CA.

*X.D. Tan and C.J. R. Shi, "Parametric analog behavioral modeling based on cancellationfree DDDs", Proc. IEEE International Workshop on Behavioral Modeling and Simulation , Santa Rosa, CA, Oct. 2002.
2001:

C.J. R. Shi and X.D. Tan, "Compact representation and efficient generation of sexpanded symbolic network functions for computeraided analog circuit design,"
IEEE Trans. on ComputerAided Design,
vol. 20, no. 7, pp. 813827, July 2001.

*Y. Wang, V. Jandhyala, and C.J. R. Shi, "Coupled electromagneticcircuit simulation of arbitrarilyshaped conducting structures," pp. 233236 in
Proc. IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP'01), Oct. 2001, Boston, MA.

V. Jandhyala, Y. Wang, D. Gope, S. Chakaraborty, and C.J. R. Shi, "A surfaceintegral equationbased technique for general coupled circuitelectromagnetic simulation," in
Proc. Progress in Electromagnetics Research Symp., Boston, July 2002.

D. Gope, S. Chakraborty, Y. Wang, V. Jandhyala, and C.J. R. Shi, "A surfacebased 3D coupled circuitelectromagnetic simulator with accurate lossy conductor modeling," in Proc. IEEE APSURSI, San Antonio, June 2002.

A. Manthe and C.J. R. Shi, ``Lowerbound based DDD minimization for efficient symbolic circuit analysis", pp. 374  379 in
Proc. IEEE International Conf. on Computer Design (ICCD'91)
, Austin TX, Oct. 2001
(Nominated by the program committee for the Best Paper Award).

D. Lungeanu and C.J. R. Shi, ``Distributed eventdriven simulation of VHDLSPICE mixedsignal circuits", pp 302307 in
Proc. IEEE International Conf. on Computer Design (ICCD'91)
, Austin TX, Oct. 2001.

*X.D. Tan and C.J. R. Shi, ``Fast powerground network optimization using equivalent circuit modeling", pp. 550554 in
Proc. 38th IEEE/ACM Design Automation Conf. (DAC'01),
Las Vegas, NE, June 2001.
2000:

T. Pi and C.J. Shi,
``Testability analysis of
analog circuits via determinant decision diagrams",
IEICE Transactions,
vol. E83A, no. 12, pp. 26082613,
Dec. 2000.

M. W. Tian and C.J. Shi, ``Worstcase tolerance analysis of linear analog circuits using sensitivity bands",
IEEE Transactions on Circuits and SystemsI: Fundamental Theory and Applications, vol. 47, no. 8, pp. 11381145, August 2000.

X.D. Tan and C.J. Shi, ``Hierarchical symbolic analysis of analog integrated circuits
via determinant decision diagrams", IEEE Trans. ComputerAided Design, vol. 19, no. 4, pp. 401412, April 2000.

C.J. Shi and X.D. Tan, ``Canonical symbolic analysis of large analog circuits
with determinant decision diagrams", IEEE Trans. ComputerAided Design,
vol. 19, no. 1, pp. 118, Jan. 2000.

*T. Pi and C.J. R. Shi, ``Multiterminal determinant decision diagrams: a new approach to semisymbolic analysis of large analog circuits", pp. 1922 in
Proc. 37th IEEE/ACM Design Automation Conf. (DAC'00), Los Angeles, C.A. June 2000 (154 out of 445 were accepted).

Y. Wang, T. Pi and C.J. R. Shi, ``Simpleyetaccurate analytic models for deepsubmicron VLSI interconnects",
Proc. IFIP International Chip Design Automation Conf., Aug. 2000.

D. Lungeanu and C.J. R. Shi, ``Parallel and distributed VHDL simulation", pp.658662 in
Proc. Design, Automation and Test in Europe (DATE'2000), Paris, France, March 2000 (106 out of 306 were accepted as regular papers).

Y. Bourai and C.J Shi,
``Layout compaction for yield
optimization via criticalarea
minimization",
Proc. Design, Automation and Test
in Europe Conference (DATE'00),
Paris, France, March 2000.

*T. Pi and C.J. Shi,
``Analog testability analysis by determinantdecision
diagramsbased symbolic analysis",
accepted by
Asia and South Pacific Design Automation Conference (ASPDAC'2000),
Hong Kong, Jan. 2000.

*X. Tan and C.J. Shi, ``Symbolic CircuitNoise
Analysis and Modeling with Determinant
Decision Diagrams,"
Asia and South Pacific Design Automation Conference (ASPDAC'2000),
Hong Kong, Jan. 2000.
1999:

C.J. Shi and W. H. Kao, ``Guest editorialspecial
issue on behavioral modeling and simulaiton
of mixedsignal/mixedtechnology systems",
IEEE Trans. Circuits and Systems  II: Analog and
Digital Signal Processing,
vol. 46, no. 10, pp. 12611261, Oct. 1999.

C.J. Shi and W. Tian,
``Simulation and sensitivity of linear analog
circuits under parameter variations by robust interval analysis",
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 4, no. 3, July 1999.

D. Lungeanu and C.J Shi,
``Distributed simulation of VLSI systems
via lookaheadfree selfadaptive optimistic and conservative
synchronization",
accepted by IEEE/ACM International Conference
on ComputerAided Design (ICCAD'99),
San Jose, CA, Nov. 1999.
(106 out of 317 submissions
were selected)

X. Tan, C.J. Shi, D. Lungeanu, J.C. Lee and L.P. Yuan,
``Reliabilityconstrained area optimization of VLSI power/ground networks via
sequence of linear programmings",
pp. in IEEE/ACM 36th Design Automation Conference (DAC'99),
New Orleans, LA, June 2125, 1999.
(Best Paper Award.)

X. Tan and C.J. Shi, ``Interpretable symbolic smallsignal
characterization of large analog circuits
using determinant decision diagrams",
pp. 448453 in
Proc. Design, Automation and Test in Europe (DATE'99),
Munich, Germany, Mar. 1013, 1999.

Y. Bourai and C.J. Shi, ``Symmetry detection for
analog layout recycling", pp. 57 in
Proc. Asia and South Pacific Design Automation Conference (ASPDAC'99),
Hong Kong, Jan. 1821, 1999.

X. Tan and C.J. Shi, ``Balanced multilevel multiway
partitioning of large analog circuits for
hierarchical symbolic analysis", pp. 14 in
Proc. Asia and South Pacific Design Automation Conference (ASPDAC'99),
Hong Kong, Jan. 1821, 1999.
1998:

C.J. Shi and J.A. Brzozowski, ``A characterization of signed hypergraphs
and its applications to VLSI via minimization and logic synthesis",
Discrete Applied Mathematics,
vol. 89, no. 13,
pp. 223243,
Dec. 1998.

C.J. Shi, ``Entity overloading for mixedsignal abstraction in VHDL",
Journal of Information Science and Engineering, vol. 14, no.3,
pp. 633644, September 1998.

N. Godambe and C.J. Shi, ``Behaviorallevel noise modeling and jitter
simulation of phaselocked loops with faults using VHDLAMS",
Journal
of Electronic Testing: Theory and Applications (JETTA), vol. 9, no.
3, August 1998.

C.J. Shi and J.A. Brzozowski,
``Clustercover: A theoretical framework
for a class of VLSICAD optimization problems",
ACM Transactions on
Design Automation of Electronic Systems (TODAES), vol. 3, no. 1, pp. 76107,
Jan. 1998.

C.J. Shi, Fault Simulation, Chapter 3 and pp. 5592 in Analog
and MixedSignal Test, Bapiraju Vinnakota (ed.),
PrenticeHall, 1998.

C.J. Shi and W. Tian, ``Automatic test generation for linear(ized) analog
circuits under parameter variations", pp. 501506 in Proc. Asia and
South Pacific Design Automation Conference (ASPDAC'98), Tokyo, Japan,
Feb. 1013, 1998. (Nominated by the program committee for the Best Paper
Award.)

W. Tian and C.J. Shi, ``Efficient DC fault simulation of nonlinear analog
circuits", pp. 899904 in Proc. Design, Automation and Test in Europe
Conference and Exhibition (DATE'98), Paris, France, Feb. 2326, 1998.
(merged EuroDAC and ED&TC conferences.) ( 122 out of 448 submissions
were selected)

X. Tan and C.J. Shi, ``Hierarchical symbolic analysis of large analog
circuits with determinant decision diagrams", pp. 318321 in Proc. IEEE
International Symposium on Circuits and Systems, vol. VI, 1998.

W. Tian and C.J. Shi, ``Worstcase analysis of linear analog circuits
using sensitivity bands", pp. 110113 in Proc. IEEE International Symposium
on Circuits and Systems, vol. VI, 1998.

W. Tian and C.J. Shi, ``Nonlinear Analog DC Fault Simulation by OneStep
Relaxation", pp. 126131 in Proc. 16th IEEE VLSI Test Symposium,
Hyatt Regency Monterey, Monterey, CA, April 2630, 1998.
(Best Paper Award.)

C.J. Shi and X. Tan, ``Efficient derivation of exact sexpanded symbolic
expressions for behavioral modeling of analog circuits", pp. 463466 in
Proc. IEEE Custom Integrated Circuits Conference, San Diego, CA,
May 1214, 1998.
1997:

C.J. Shi, A. Vannelli and J. Vlach, ``Performancedriven layer assignment
by integer linear programming and pathconstrained hypergraph partitioning",
Journal of Heuristics, vol. 3, no. 3, pp. 225243, November 1997.

C.J. Shi and W. Tian, Simulation and Sensitivity of Linear(ized) Analog
Circuits under Parameter Variations, Chapter 44 and pp. 540551 in
VLSI: Integrated Systems on Silicon, Ricardo Reis and Luc Claesen
(eds.), Chapman & Hall, 1997;
also in Proc. 9th IFIP International
Conference on Very Large Scale Integration (VLSI'97), Gramado, BRAZIL,
August 2629, 1997.

C.J. Shi, ``Blocklevel fault isolation using partition theory and logic
minimization techniques", pp. 319324 in Proc. Asia and South Pacific
Design Automation Conference (ASPDAC'97), Chiba, Japan, Jan. 2831,
1997.

C.J. Shi, ``Solving constrained via minimization by compact linear programming",
pp. 635640 in Proc. Asia and South Pacific Design Automation Conference
(ASPDAC'97), Chiba, Japan, Jan. 2831, 1997.

N. Godambe and C.J. Shi, ``Behaviorallevel noise modeling and jitter
simulation of phaselocked loops with faults using VHDLAMS", pp. 177183
in Proc. IEEE VLSI Test Symp. (VTS'97), Monterey, CA, April 27 
30, 1997 (62 out of 178 submissions were accepted).

W. Tian and C.J. Shi, ``Rapid frequencydomain analog fault simulation
under parameter tolerances", pp. 275  280 in Proc. IEEE/ACM Design
Automation Conference (DAC'97), Anaheim, CA, June 913, 1997 (139
out of 389 submissions accepted).

C.J. Shi, ``Blocklevel fault isolation for mixedsignal multichip modules
under parameter varations", IEEE/IMAPS MCM Test IV Workshop, Napa
Valley, California, Sept. 14  17, 1997.

C.J. Shi, Y. Ye and X. Tan, ``Behavioral model optimization via sensitivityenhanced
genetic search", pp. 1724 in Proc. IEEE/VIUF International Workshop
on Behavioral Modeling and Simulation, Washington DC, Oct. 1997.

C.J. Shi and X. Tan, ``Symbolic analysis of large analog circuits with
determinant decision diagrams", pp. 366373 in Proc. IEEE/ACM International
Conference on ComputerAided Design, (ICCAD'97), San Jose, CA, November
913, 1997. ( 102 out of 341 submissions were accepted.)
1996:

O. Coudert and C.J. Shi, ``Exact multilayer topological planar routing",
pp. 179182 in Proc. IEEE Custom Integrated Circuit Conference (CICC'96),
San Diego, CA, May 58, 1996.

C.J. Shi, ``Finding a minimal test set for analog fault diagnostic dictionary",
pp. 303308 in Proc. International Workshop on ComputerAided Design,
Test, and Evaluation for Dependability, Beijing, China, July 23, 1996.

C.J. Shi, ``Fault isolation for mixedsignal multichip modules", in IEEE
MCM Test II Workshop, Napa Valley, California, Sept. 15  18, 1996.

C.J. Shi, ``Entity overloading for mixedsignal abstraction in VHDL",
pp. 562567 in Proc. European Design Automation Conference (EuroDAC/EuroVHDL'96),
Geneva, Switzerland, September 1620, 1996. (Nominated by the program
committee for the Best Paper Award.)

C.J. Shi and N. Godambe, ``Behavioral fault modeling and simulation of
phaselocked loops using a VHDLA like language", pp. 245250 in Proc.
IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester,
N.Y., September 2327, 1996. (Acceptance Ratio: 0.5)

C.J. Shi, A. Vannelli and J. Vlach, ``Performancedriven layer assignment
for printed circuit boards and integrated circuits", pp. 171174 in Proc.
IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester,
N.Y., September 2327, 1996. (Acceptance Ratio: 0.5)

O. Coudert and C.J. Shi, ``Exact dichotomybased constrained encoding",
pp. 426431 in Proc. IEEE International Conference on Computer Design
(ICCD'96), Austin, Texas, October 79, 1996.
19881995:

C.J. Shi and A. Vachoux, VHDLAMS Design Objectives and Rationale,
Chapter 1 and pp. 130 in Modeling in Analog Design, vol. 2 in Series
Current Issues in Electronic Modeling (CIEM), JeanMichel Berge,
Oz Levia and Jacques Rouillard (eds.),
Kluwer Academic Publishers, 1995.

C.J. Shi and J. A. Brzozowski, ``A framework for the analysis and design
of algorithms for a class of VLSI optimization problems", pp. 6774 in
Asia and South Pacific Design Automation Conference (ASPDAC'95),
Aug. 29  Sept. 1, 1995. (Nominated by the program committee for the
Best Paper Award.)

C.J. Shi, E. Christen, P. Liebmann, S. Krolikoski, and W. Zhou, ``VHDLA:
Analog extension to VHDL", pp. 160165 in Proc. IEEE International ASIC
Conference & Exhibit, Sept. 1994.

C.J. Shi and J.A. Brzozowski, ``An efficient algorithm for constrained
encoding and its applications", IEEE Trans. ComputerAided Design,
vol. 12, no. 12, pp. 18131826, Dec. 1993.

C.J. Shi, ``Analysis, sensitivity and macromodeling of the Elmore delay
in linear networks for performancedriven VLSI design", International
Journal of Electronics, vol.75, no.3, pp.467484, Sept. 1993.

C.J. Shi, Constrained Via Minimization and Signed Hypergraph
Partitioning, pp. 337356 in Algorithmic Aspects of VLSI Layouts,
D. T. Lee and M. Sarrafzadeh (eds.), World Scientific Publishing Company,
1993.

C.J. Shi, ``Towards a unified operational semantics for behavior specification
of VLSI systems", International Workshop on ComputerAided CoDesign,
Cambridge, Massachusetts, Oct. 78, 1993.

C.J. Shi, A. Vannelli and J. Vlach, ``An improvement on Karmarkar's algorithm
for integer programming", COAL Bulletin of the Mathematical Programming
Society, vol.21, pp. 2328, 1992.

C.J. Shi, ``A signed hypergraph model of constrained via minimization",
Microelectronics Journal, vol.23, no.7, pp.533542, Nov. 1992.

C.J. Shi and J.A. Brzozowski, ``Efficient constrained encoding for VLSI
sequential logic synthesis", pp. 266271 in Proc. First European Design
Automation Conf., Hamburg, Germany, Sep. 1992. (79 papers out of 335
were accepted.)

C.J. Shi, ``A signed hypergraph model of constrained via minimization",
pp. 159166 in Proc. Second Great Lakes Symp. on VLSI, Kalamazoo,
MI, Feb. 1992.

C.J. Shi and A. Vannelli, ``An improvement on Karmarkar's algorithm
for integer programming", in the Sixth SIAM Conference on Discrete Mathematics,
Vancouver, June 1992.

J. Vlach, J. Barby, A. Vannelli, I. Talkhan, and C.J. Shi, ``Group delay
as an estimate of delay in logic", IEEE Trans. ComputerAided Design,
vol.10, no.7, pp. 949953, July 1991.

C.J. Shi, ``Modeling kway splits of physical routings for constrained
via minimization", pp. 4B.5.14B.5.8 in Proc. 1991 Canadian Conf. on
VLSI, Aug. 1991.

W.Q. Zhao and C.J. Shi, Schematic Capture and Automatic Generation
of Circuit Diagrams, Chapter 1 and pp. 127 in Computer Aided Design
of VLSI Circuits: Theory and Methods, P. Tan (ed.), Fudan University
Press, 1990.

C.J. Shi, A. Vannelli, and J. Vlach, ``A hypergraph partitioning approach
to the via minimization problem", pp. 2.7.12.7.8 in Proc. 1990 Canadian
Conf. on VLSI, Oct. 1990.

Y. Liu and C.J. Shi, ``Piecewise delay modeling of MOS VLSI digital
circuits", Research & Progress of Solid State Electronics, vol.8,
no.4, pp.438442, 1988.

C.J. Shi and K. Zhang, ``Tree relaxation: a new iterative solution method
for linear equations", pp. 23552359 in Proc. IEEE Int. Symp. on Circuits
and Systems, June 1988.

C.J. Shi and K. Zhang, ``A robust approach to timing verification",
pp. 5659 in Proc. IEEE/ACM Int. Conf. ComputerAided Design (ICCAD'87),
Nov. 1987. (119 papers out of 440 were accepted.)

C.J. Shi and K. Zhang, ``A newly defined signal delay time and its basic
theory", pp. 142146 in Proc. IEEE Asian Electronics Conference,
Hong Kong, September 1987.