VLSI Design and CAD Laboratory

Department of Electrical Engineering
University of Washington , Box 352500
Seattle, WA 98195-2500 USA
Phone: +1 (206) 685-8678

The VLSI Design and CAD Laboratory researches topics related to digital circuit design and computer-aided design for very large scale integrated circuits. The director of the lab is Carl M. Sechen.

Current Research:

• High Speed Design in Output Prediction Logic
• Clock Generation and Distribution for Output Prediction Logic
  
• Power-Delay-Area Optimized Digital Design Flow
• Standard Cell Design for Regularity
  
• Transistor-level Sizing with Convex Delay Models
• Locally Clocked Logic
• Radiation Hard Design

Recent Papers:

• S. Sun, Y. Han, X. Guo, K. H. Chong, L. McMurchie, and C. Sechen, "409ps 4.7FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS",  ISVLSI 2005, Tampa, Florida
  
• Y. Han, L. McMurchie, C. Sechen, "A High Performance CMOS Programmable Logic Core", Custom Integrated Circuits Conference 2004
  
• L. McMurchie and C. Sechen, "RADAR - Reconfigurable Analog and Digital Array for Radiation-Hardened Circuits",  Aerospace Conference 2004
  
• M. Vujkovic, D. Wadkins, B. Swartz and C. Sechen, "Efficient timing closure without timing driven placement and routing", DAC 2004, San Diego, California
• S. Kio, K. H. Chong and C. Sechen, "A low power delayed-clocks generation and distribution system", International Simposium on Circuits and Systems (ISCAS) 2003, Bangkok, Thailand
  
• J. Ciric-Vujkovic and C. Sechen, "Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 5, May 2003
• H. Tennakoon and C. Sechen, "Gate Sizing Using Lagrangian Relaxation Combined with a Fast Gradient-Based Pre-Processing Step", ICCAD 2002, San Jose, California
  
• L. McMurchie and C. Sechen, "WTA - Waveform-Based Timing Analysis for Deep Submicron Circuits", ICCAD 2002, San Jose, California
• M. Vujkovic and C. Sechen, "Optimized Power-Delay Curve Generation for Standard Cell ICs", ICCAD 2002, San Jose, California
• G. N. Hoyer, G. Yee and C. Sechen, "Locally-Clocked Pipelines and Dynamic Logic", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 1, February 2001
  
• S. Sun, L. McMurchie and C. Sechen, "A High-Performance 64-bit Adder Implemented in Output Prediction Logic", 19th Conf. on Advanced Research in VLSI (ARVLSI), 2001, Salt Lake City, Utah
• S. Kio, L. McMurchie and C. Sechen, "Application of Output Prediction Logic to Differential CMOS",  IEEE Computer Society Workshop on VLSI 2001, Orlando, Florida
  
• T. Serdar and C. Sechen, "Automatic Datapath Tile Placement and Routing", DATE 2001,  Munich, Germany
• L. McMurchie, S. Kio, G. Yee, T. Thorp, C. Sechen, "Output Prediction Logic: A High-Performance CMOS Design Technique", ICCD 2000, Austin, Texas
• J. Ciric-Vujkovic and C. Sechen, "Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic", DATE 2000, Paris, France
  

Lab personnel and their research areas

Photo Gallery