| Faculty |
Research Area |
| Carl M. Sechen |
|
| Larry McMurchie | High Performance Reconfigurable and Reliable Computing |
|
|
|
| Kian Haur Chong | Clock Generation for Output Prediction Logic |
| Xinyu
Guo |
High Speed Division |
| Ryan
Kruse |
Standard Cell Design for Regularity |
| James Lan | Radiation-Hard Design |
| Salim Rabaa | Locally-Clocked Logic |
| Sheng Sun | High
Performance OPL Adders and Power Efficient Static CMOS Adders |
| Hiran Tennakoon | Transistor-level Sizing with Convex Delay Models |
| Miodrag Vujkovic | Power-Delay-Area Optimized Digital Design Flow |
| David Wadkins | Standard Cell Generation |
| Jinyao Zhang | Performance Analysis of Different Multiplier
Architectures |
|
|
|
| Tatjana Serdar | Transistor-level placement |
| Tyler Thorp | Dynamic Logic Synthesis/Placement |
| Gin Yee | Dynamic logic synthesis and design using CD Domino |
| Yi Han | OPL-based FPGA |
| Ruxandra-Dana Albu | High-Speed Multiplier Implemented in OPL |
| Gregg Hoyer | Locally-Clocked (LC) Dynamic
Logic |
| Jovanka Ciric-Vujkovic | Dynamic Logic Synthesis |
| Samuel Kio | Output Prediction Logic (OPL) |
Department
of
Electrical Engineering
University of
Washington
Box 352500
Seattle, WA 98195-2500
(206) 685-8678, 616-3169 voice, (206) 543-3842 FAX