Place and Route Techniques for FPGA Architecture Advancement


The advent of Field Programmable Gate Arrays (FPGAs) is a strong indication of current needs for affordable, flexible, high performance computing devices. While the flexibility of FPGAs is comparable to that of conventional microprocessors, FPGAs sometimes produce performance wins, especially for applications that directly benefit from spatially parallel hardware implementations. Yet, FPGAs continue to remain bigger, slower and more power hungry when compared to application specific custom logic.

In order to bridge performance gaps between FPGAs and other computational devices, FPGA architectures have been widely researched over the past decade. These research efforts have clearly shown that the careful development of Computer Aided Design (CAD) algorithms is an important step in extracting performance benefits from FPGAs. Our research focuses on the development of FPGA CAD algorithms, and is divided into two topics. The first deals with the development of a routing algorithm for pipelined FPGAs, while the second focuses on architecture-adaptive FPGA placement algorithms.