Visvesh Sathe

Visvesh Sathe received the B.Tech degree in Electrical Engineering from the Indian Institute of Technology, Bombay, and the MS and PhD degrees from the University of Michigan, Ann Arbor Prior to joining the faculty at the UW. In 2007 he joined Advanced Micro Devices his research focused on inventing and developing new technologies for next-generation microprocessors. Sathe led the research and development effort at AMD that resulted in the first-ever resonant clocked commercial microprocessor. In addition, several of his other inventions in the area of high-speed digital design, low-power processing, and adaptive clocking for supply droop mitigation have been adopted for use in future-generation microprocessors. joined the University of Washington. In 2013, he joined the Department of Electrical & Computer Engineering at the University of Washington where his group conducts research over a variety of areas covering circuits and architectures for low power computing and biomedical systems. His areas of interests span digital, mixed-signal and integrated power circuits, with an emphasis on exploiting computing and system-circuit-technology co-design for enhancing system capabilities. He serves as a member of the Technical Program Committees of the Custom Integrated Circuits Conference (CICC) and the Technical Program sub-committe chair for digital and analog circuits at the Design Automation Conference (DAC). He has previously served as a guest editor for the Journal of Solid-State Circuits, and is currently serving on the Solid State Circuits Society (SSCS) Webinar committee. He is an SSCS distinguished lecturer for 2021-2022.

1. AMD Vice-President Spotlight Award for the research, development, and translation of resonant-clocking into volume microprocessor production, 2012.
2. NSF CAREER Award 2019
3. Intel Outstanding Researcher Award, 2020
4. Distinguished Lecturer, Solid-State Circuits Society 2021-2022

• Bidirectional Brain Computer Interfaces : Circuits and Architectures (NSF)
• Enhancing High Performance Computing through Low Temperature Logic Technologies (DARPA)
• Runtime computation for advancing integrated circuits and systems (NSF, SRC)
• Low-footprint, voltage scalable thermal sensor systems (Intel)
• Adaptive circuits and architectures for hardware security (Intel)
• Power Management : Run-time configurable voltage regulator circuits and architectures (Intel)
• High-performance, energy-efficient optimal beamforming baseband processors for digital mm-Wave communication (JCATI, Boeing)
• Advanced clocking techniques for high performance and energy efficient digital systems (Qualcomm)

• C-H. Huang, A. Mandal, D. Pena-Colaiocco, E. Pereira and V. S. Sathe, "Energy Minimization of Duty Cycled Domains through Domain Decoupling Capacitance Energy Recycling and Autonomous Energy Tracking”, to appear, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022.
• D. Pena-Colaiocco, C-H. Huang, K-D. Chu, J. C Rudell and V. S. Sathe, " An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS”, to appear, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022.
• Huang, Chi-Hsiang, et al. "A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS." 2021 IEEE International Solid-State Circuits Conference (ISSCC). Vol. 64. IEEE, 2021.
• Mandal, Arindam, et al. "A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation." 2021 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2021.
• X. Sun, A. Boora, W. Zhang, R. Pamula and V. S. Sathe," A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS", ISSCC 2019
• F. Rahman, R. Pamula, A. Boora and V. S Sathe, "Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS", ISSCC 2019
• S. Kim, T. Moreau, P. Howe, A. Alaghi, L. Ceze and V. S. Sathe, "Energy Efficient Neural Network Acceleration under Bit-level Memory Errors", Transactions on Circuits and Systems-1, 2018
• F. Rahman, S. Kim, N. John, R. Kumar, R. Pamula and V. S. Sathe, "An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor", VLSI Symposium 2018
• R. Pamula, S. Kim, X. Sun, F. Rahman and V. S. Sathe, "An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS", VLSI Symposium 2018
• X. Sun, S. Kim, F. Rahman, R. Pamula, X. Li, N. John, and V. S. Sathe, "A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor", ISSCC 2018
• F. Rahman, G. Taylor, V. S. Sathe, "Computational Locking: Accelerating Lock-times in All-Digital PLLs", VLSI Symposium 2017
• W. A. Smith, J. P. Uehlin, J. C. Rudell, V. S. Sathe, "A Scalable, Highly-Multiplexed Delta-Encoded Digital Feedback ECoG Recording Amplifier with Common and Differential-Mode Artifact Suppression", VLSI Symposium 2017

Post Doctoral Scholars

• Rajesh Pamula
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Current Students:

• Chi-Hsiang Huang (PhD)
• Arindam Mandal (PhD)
• Diego Pena Colaiocco (PhD)
• Kevin Dario Patino Sosa (PhD)
• Julian Arturo Arenas (PhD)
• Jung Jin Park (PhD)
• Ryan Wang (MS)
• Ansh Joshi (MS)
• Peter Zhong (BS)
• An Nguyen (BS)