Current Projects | Recently Completely Projects | Completely Projects

Current Projects

  • SRC: Test Generation for Mixed-Signal Design Verification and Post-Silicon Debugging

    Sponsor : SRC
    PIs: Richard Shi
    Period: Sept.2013 to Sept 2016
    People: Coming Soon.
    Objectives:Mixed-Signal design verification and post-silicon debugging processes rely heavily on the use of various circuit simulators. The total simulation and debugging time depend on both CPU time per simulation run and the simulation test vector (stimulus) length. Existing work has primarily focused on fast simulation algorithms and simulation with multiple CPU cores to reduce CPU time per simulation. The objective of this project is the development of systematic methods of deriving the minimal length simulation tests for mixed-signal functional verification and post-silicon debugging.


    Sponsor : JCATI/Boeing project
    PIs: Richard Shi
    Period: to 2014
    People: John P. Uehlin, Wenbin Xu, Bijan Shirazi-Wu, Jerry Lopez, *Jeremy Popp
    Objectives: To design an optical receiver unit towards enabling the use of low cost and light weight plastic optical communications in airplane avionics backplanes. The design directly targets the high sensitivity and low cost necessary for working with plastic optical fiber mediums.

Recently Completed Projects

  • JCATI: An Optical Tranceiver using 65nm process with CMOS Technology

    Sponsor : State of Washington
    PIs: Richard Shi
    Period: Feb 08, 2013 to Jun 30, 2013
    Objectives: The purpose of this project is to enable use of low cost and light weight plastic fiber based optical communications in airplane avionics communications backplanes. This is part of the Joint Center for Aerospace Technology Innovation.

  • CASCADE: A 40Gbps Low-Density Parity-Check Decoder ASIC in 3-Dimensional Integrated Circuit Technology

    Sponsor : DARPA and SPAWAR
    PIs: Richard Shi
    Period: Spe 30, 2005 to Sep 29, 2009
    Collaborators: MIT Lincon Lab
    Objectives: To design, implement and test a 40Gbps LDPC communication decoder using emering three-dimensional (multiple layers of transistors) technologies. The research focuses are on the development of structured 3D design methodologies, design flow and CAD tools to enable 3D ASIC design and the demonstration of the potential of fine-grained 3D device interconnect technologies in extending Moore's Law.

  • CoSMoS: Coupled Modeling and Simulation of Systems-on-Chips

    Sponsor : DARPA
    PIs: Richard Shi, Vikram Jandhyala, David Allstot
    Subcontractors: Lawrence Livermore National Lab., Boeing
    Period: July 1, 2001 to June 30, 2004
    Industry Collaborators: Motorola, Intel
    Objectives: a coupled hierarchical modeling and fast simulation capacities for systems-on-chip signoff simulation with the emphasis on predicting substrate coupling and full-wave power-ground noises Target Applications: multiple transceivers on chips.

  • NSF CAREER: Behavioral Modeling and Simulation

    Sponsor : NSF
    PIs: Richard Shi
    Period: July 1, 2001 to June 30, 2004
    Objectives: Methods and algorithms for automatic behavioral modeling and simulation.

  • Symbolic Circuit Analysis and Modeling of Analog/RF Circuits

    Sponsor : DARPA
    PIs: Richard Shi
    Period: July 1, 2001 to June 30, 2004
    Industry Collaborators: Motorola, Intel
    Objectives: Symbolic analysis of analog/RF circuits Target Applications: analog/RF circuit block modeling.

  • Application of Communication Theory to Nano Interconnect Modeling

    Sponsor : NSF/SRC
    PIs: Richard Shi, Sumit Roy and David Allstot
    Period: July 1, 2001 to June 30, 2004
    Objectives: To develop models, based on communication principles for interconnects on a noise environment, and to apply developed models to on-chip signaling.

  • Modeling for SoC Integration

    Sponsor : NSF
    PIs: Richard Shi, and David Allstot
    Period: July 1, 2001 to June 30, 2004
    Objectives: Create behavioral models for analog/RF blocks.

  • Fast Methods for Coupled Circuit/EM/Digital Simulation

    Sponsor : NSF/SRC
    PIs: Richard Shi and Vikram Jandhyala
    Period: July 1, 2001 to June 30, 2004
    Objectives: Methods and algorithms for fast simulation of coupled EM, circuit-level and logic-level model.

Completed Projects

  • Layout-Dependent Substrate Modeling via Symbolic Network Reduction (SRC)

  • Application of Communication Principles to Nano-Interconnect Research (NSF)

  • Behavioral Modeling and Simulation for Mixed-Signal/Mixed-Technology Systems (NSF CAREER)

  • Modeling, Simulation and Optimization of Deep-Submicron Interconnect for Performance and Manufacturability (UW)

  • AWECAD: A Web-enabled Environment for Collaborative Analysis and Design of Mixed-Signal/Mixed-Technology Systems (NASA, UW)

  • Symbolic Analysis and Automated Modeling of Analog Integrated Circuits (DARPA, Rockwell)

  • Circuit Simulation and Characterization Considering Process Variations (DARPA)

  • Deep-Submicron Analog Layout Automation through Automating Design Reuse for Performance and Manufacturability (CDADIC, DARPA)

  • Distributed and Parallel Simulation of VLSI Circuits and Systems including Mixed-Technology Components (DARPA)

  • Fault Modeling, Simulation and Test Generation for Mixed-Signal Circuits (DARPA)

  • Mixed-Signal Hardware Description Language VHDL-AMS (DARPA)