UWEE Tech Report Series

Multi-Level Symmetry Constraint Generation for Retargeting Large Analog Layouts


UWEETR-2004-0004

Author(s):
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono and C-J. Richard Shi

Keywords:
VLSI layout, symmetry, analog design

Abstract

The strong impact of layout intricacies on analog circuit performance poses great challenges to analog layout automation. Recently, template-based methods have been shown to be effective in reuse- centric layout automation for CMOS analog blocks such as operational amplifiers. The layout-retargeting method first creates a template by extracting a set of constraints from an existing layout representation. From this template, new layouts are then generated corresponding to new technology processes and new device specifications. For large analog layouts, however, this method results in an unmanageable template due to a tremendous increase in the number of constraints, especially those emerging from layout symmetries. In this paper, we present a new method of multi-level symmetry constraint generation by utilizing the inherent circuit structure and hierarchy information from the extracted netlist. The method has been implemented in a layout-retargeting system called IPRAIL and demonstrated 18 times reduction in the number of symmetry constraints required for retargeting an Analog-to-Digital converter layout; this enables our retargeting engine to successfully handle the complexities associated with large analog layouts. While manual re-layout is known to take weeks, our layout-retargeting tool generates the target layout in hours and achieves comparable electrical performance.

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