Determinant-Decision-Diagram (DDD) based Symbolic Circuit Analysis

PI | Students | Sponsors | Publications

Principal Investigator

Richard Shi

Participating Students:

Xiangdong Tan (1996-1999; Now Associate Professor, University of California, Riverside)
Tao Pi (1998-1999; Now with Xilinx)
Alicia Manthe (1999-2003; Now with Amazon)
Zhao Li (1999-2005; Now with Cadence Design Systems)
Sambuddha Bhattacharya (1999-2005; Now with Synopsys)
Guoyong Shi (2002-2005; Now Full Professor, Shanghai Jiao Tong University, School of Microelectronics)
Bo Hu (2002-2005, Now with Cadence Design Systems, San Jose, CA)

DARPA EP&I Program (1996-2001)
DARPA NeoCAD Program (2002 to 2004)
NSF CAREER Award
SRC

• C.-J. Shi and X.-D. Tan, ``Canonical symbolic analysis of large analog circuits with determinant decision diagrams", IEEE Trans. Computer-Aided Design, vol. 19, no. 1, pp. 1-18, Jan. 2000.
• G. Shi, B. Hu, and C.-J. R. Shi, "On symbolic model order reduction", IEEE Trans. on Computer-Aided Design, vol. 25, no. 7, pp. 1257-1272, July 2006.
• X.-D. Tan and C.-J. R. Shi, "Efficient approximation of symbolic expressions for analog behavioral modeling and analysis," IEEE Trans. on Computer-Aided Design, vol. 23, no. 6, pp. 907-918, June 2004.
• X.-D. Tan and C.-J. R. Shi, "Efficient DDD-based interpretable symbolic characterization of large analog circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 3119-3126, Dec. 2003.
• C.-J. R. Shi and X.-D. Tan, "Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design," IEEE Trans. on Computer-Aided Design, vol. 20, no. 7, pp. 813-827, July 2001.
• T. Pi and C.-J. Shi, ``Testability analysis of analog circuits via determinant decision diagrams", IEICE Transactions, vol. E83-A, no. 12, pp. 2608-2613, Dec. 2000.
• X.-D. Tan and C.-J. Shi, ``Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams", IEEE Trans. Computer-Aided Design, vol. 19, no. 4, pp. 401-412, April 2000.
• T. Pi and C.-J. Shi, ``Testability analysis of analog circuits via determinant decision diagrams", IEICE Transactions, vol. E83-A, no. 12, pp. 2608-2613, Dec. 2000.
• A. Manthe, Z. Li, and C.-J. R. Shi, "Symbolic analysis of analog circuits with hard nonlinearity", pp. 542-545 in Proc. IEEE/ACM Design Automation Conf. (DAC'03), June 2003 (acceptance ratio: 25%).
• S. Bhattacharya and C.-J. R. Shi, "Concurrent gate and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis," pp. 660-663 in Proc. IEEE International Symp. on Circuits and Systems (ISCAS'03), vol. 4, May 2003.
• A. Manthe, Z. Li, C.-J. R. Shi and K. Mayaram, "Symbolic analysis of nonlinear analog circuits," pp. 1108-1109 in Proc. Design, Automation and Test in Europe Conf. (DATE'03), Munich, Germany, March 2003.
• *X.-D. Tan and C-.J R. Shi, "Efficient DDD-based term generation algorithm for analog behavioral modeling," pp. 789-794 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'03), Japan, Jan. 2003.
• A. Manthe and C.-J. R. Shi, "Finding minimal symbolic expressions for analog modeling", in Proc. IEEE International Conf. on Communications, Circuits and Systems (ICCCAS'02), June 29-July, 2, 2002.
• X.-D. Tan and C.-J. R. Shi, "Parametric analog behavioral modeling based on cancellation-free DDDs", Proc. IEEE International Workshop on Behavioral Modeling and Simulation , Santa Rosa, CA, Oct. 2002.
• A. Manthe and C.-J. R. Shi, ``Lower-bound based DDD minimization for efficient symbolic circuit analysis", pp. 374 - 379 in Proc. IEEE International Conf. on Computer Design (ICCD'91) , Austin TX, Oct. 2001 (Nominated by the program committee for the Best Paper Award).
• T. Pi and C.-J. R. Shi, ``Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of large analog circuits", pp. 19-22 in Proc. 37th IEEE/ACM Design Automation Conf. (DAC'00), Los Angeles, C.A. June 2000 (154 out of 445 were accepted).
• *T. Pi and C.-J. Shi, ``Analog testability analysis by determinant-decision diagrams-based symbolic analysis", accepted by Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 2000.
• X. Tan and C.-J. Shi, ``Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams," accepted by Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 2000.
• *X. Tan and C.-J. Shi, ``Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams", pp. 448-453 in Proc. Design, Automation and Test in Europe (DATE'99), Munich, Germany, Mar. 10-13, 1999.
• *X. Tan and C.-J. Shi, ``Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis", pp. 1-4 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 18-21, 1999.
• *X. Tan and C.-J. Shi, ``Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams", pp. 318-321 in Proc. IEEE International Symposium on Circuits and Systems, vol. VI, 1998.
• *C.-J. Shi and X. Tan, ``Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits", pp. 463-466 in Proc. IEEE Custom Integrated Circuits Conference, San Diego, CA, May 12-14, 1998.
• *C.-J. Shi and X. Tan, ``Symbolic analysis of large analog circuits with determinant decision diagrams", pp. 366-373 in Proc. IEEE/ACM International Conference on Computer-Aided Design, (ICCAD'97), San Jose, CA, November 9-13, 1997. ( 102 out of 341 submissions were accepted.)

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