People > Faculty

Scott Hauck

Scott Hauck
Professor
VLSI and Digital Systems
307Q EE/CSE
Box 352500
University of Washington
Seattle, WA 98195

Phone: (206) 221-5119
E-mail: hauck@ee.washington.edu

University of Washington, CSE, 1995 Ph.D., 1992 MS
University of California-Berkeley, EECS, 1990 B.S.

[Biosketch] [Honors] [Research Interests] [Selected Publications] [Patents] [Current Grad Students] [Teaching]

Biosketch

He is a Professor at the University of Washington's Department of Electrical Engineering, in the Embedded Systems and VLSI group, and an Adjunct in the Department of Computer Science and Engineering. His work is focused around FPGAs, chips that can be programmed and reprogrammed to implement complex digital logic. His interests are the application of FPGA technology to situations that can make use of their novel features: high-performance computing, reconfigurable subsystems for system-on-a-chip, computer architecture education, hyperspectral image compression, and other areas. His work encompasses VLSI, CAD, and applications of these devices. He is editor (with Andre' DeHon) of a book on reconfigurable computing: Scott Hauck, Andre' DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

In 2010 he won the University of Washington
Distinguished Teaching Award.

He is the director of the Adaptive Computing
Machines and Emulators Lab.

Honors

FCCM20: Highlights of the First Twenty Years of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2013. 4 of 25 papers in this volume - most of any author:

S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, "The Chimaera Reconfigurable Functional Unit", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.
S. Hauck, Z. Li, E. J. Schwabe, "Configuration Compression for the Xilinx XC6200 FPGA", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 138-146, 1998.
Z. Li, K. Compton, S. Hauck, "Configuration Cache Management Techniques for FPGAs", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 22-36, 2000.
P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, D. Zaretsky, "A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 39-48, 2000.

IEEE Symposium on Field-Programmable Custom Computing Machines, Best Paper Award, 2012
2011 U.W. Dept. of Electrical Engineering Faculty Service Award
2010 University of Washington Distinguished Teaching Award
2009 College of Engineering Faculty Innovator: Teaching & Learning
Finalist, U.W. Distinguished Teaching Award, 2008
Best Paper Award, Microelectronic Systems Education Conference, 2007.
Elixent, Inc. S.O.A.P.-Star: Spot On Award Program (employee achievement award), 2006.
Alfred P. Sloan Research Fellow (2001)
U.W. EE Department's Outstanding Research Advisor Award 2001
Senior Member, ACM (2009)
Senior Member, IEEE (2001)
June and Donald Brewer Junior Professorship, (Northwestern chair, given up in move to U.W.) 1999-2001
NSF CAREER award (1999)
1999 IEEE Circuits and Systems Society Transactions on VLSI Systems Best Paper Award
Northwestern University, ECE Department's Best Teacher of 1998/99
AT&T Bell Laboratories Graduate Fellowship
National Merit Finalist
Nominated, U.W. College of Engineering Faculty Innovator for Teaching, 2007, 2008, 2009.
Nominated, U.W. Distinguished Teaching Award, 2004, 2007, 2008, 2009
Nominated, U.W. College of Engineering Outstanding Faculty Member, 2004
Nominated, U.W. EE Department's Faculty Service Award, 2004
Nominated, U.W. EE Department's Outstanding Research Advisor Award 2003, 2004, 2008, 2009
Nominated, U.W. EE Department's Teaching Award 2001, 2003, 2007

Honors to students/advisees

College of Engineering Community Innovators Teaching Assistant Innovator Award to Ken Eguro (2008)
Department of Electrical Engineering Graduate Teaching Award to Ken Eguro (2007)
Yang Research Award to Akshay Sharma (2005), Mike Haselman (2010).
Mary Gates Endowment for Students research training grant to Henry Lee (2003)
Intel Fellowship to Mark Chang (2002)
Lincoln Labs Fellowship to Shawn Phillips (2002)
Cabell Thesis Year Fellowship to Katherine Compton (2002)
U.W. EE Department's Outstanding Research Assistant Award to Mark Chang (2001-2002)
National Science Foundation Fellowships to Katherine Compton (1998), Mark Holland (2001), Nathaniel McVicar (2011)
1999 Motorola UPR Best Paper Award (to student Katherine Compton)
National Science Foundation Fellowship Honorable Mention to Michael Beauchamp (2003 & 2004), Nathaniel McVicar (2010)

Research Interests

Reconfigurable Subsystems for System-on-a-Chip; FPGA Architectures, CAD tools, Compilers, and Applications; VLSI Design & CAD.

Research Projects

Bioaccelerator
Development of high-speed genome resequencing and related bioinformatics/genomics algorithms on reconfigurable logic.
Elan
Development of an object-oriented model for programming large-scale hybrid FPGA and CPU reconfigurable computing systems.
Mosaic: Coarse-grained reconfigurable arrays
Creation of power-efficient programmable fabrics and CAD flows using ALU-based computation units, heavily pipelined bus-based interconnects, and time-multiplexing.
FPGA-Based Medical Imaging in the MiCES System
Development of a high-performance PET scanner for animals and humans. Uses a large system of FPGAs to help detect photons emitted from radioactive materials injected into a host organism.

Previous Research Efforts

VHDL and ImpulseC Acceleration of Tomography
Using the acceleration of medical image reconstruction algorithms to compare hardware description languages and high-level languages for high-performance computing on FPGAs.
Heavily Pipelined Commodity FPGAs
Development of FPGA architectures and CAD tools that support mass-market commodity applications, yet still can provide huge performance increases for latency-tolerant designs.
Totem: Reconfigurable Subsystems for System-on-a-Chip
Development of domain-specific and domain-adaptive FPGA architectures, layout generation, and physical design tools for adding reconfigurable subsystems into future complex ASIC designs.
CAD for FPGAs
Development of architecture-adaptive CAD tools for FPGAs, including the architecture-adaptive placer Independence, and the pipelining-aware router PipeRoute.
FPGA Support for Floating Point Computations
Development of FPGA architectures, libraries, CAD tools, and methodologies to efficiently support floating-point computations.
FPGA Logarithmic Number System Library
A library of basic units for logarithmic number systems, as well as format conversions.
FPGA-based Hyperspectral Image Compression
A NASA-sponsored investigation into spaceborne use of FPGAs. We are developing image compression algorithms to radically reduce the bandwidth requirements for downlinking NASA hyperspectral (multiple image bands, such as IR, UV, visible light) images.
FPGA Configuration Management
Exploration of methods to radically reduce the reconfiguration overhead in FPGA devices to enable efficient run-time-reconfiguration. We are also working on an configuration architecture layout to integrate these techniques into a complete chip design.
ALICE - ACME Labs Instant Computer
Development of an FPGA-based infrastructure and curriculum for computer architecture education.
Fast CAD
Development of fast placement & routing tools for logic emulation systems.
Variable Precision Analysis
Techniques to automatically optimize the bitwidths of MATLAB specifications of future FPGA hardware designs.
The Chimaera Reconfigurable Functional Unit
Development of a reconfigurable coprocessor for general purpose computing, as well as software mapping tools to support these systems.
Adaptive Computing
A DARPA-sponsored investigation into architectures, compilers, and configuration management for mass-market adaptive computing.
The MATCH Project (MATLAB Compilation for Heterogenous Systems)
Development of an automatic compiler for MATLAB programs targetted to a heterogenous system of FPGAs, DSPs, and microprocessor.
Hybrid FPGA/DSP Architectures
Exploring the use of FPGAs for digital signal processing, including the design of new architectures and cell structures.
Field-Programmable Systems-on-a-Chip
A DARPA-sponsored effort investigating architectures for hybrid FPGA, CPU, and DSP systems on a single chip. This research is aided by NASA Goddard through applications that exploit heterogenous systems.
Distributed High-Performance Computing for VLSI/CAD
The use of high-performance ATM Network of Workstations for VLSI/CAD applications.
Multi-FPGA Systems & Rapid-Prototyping
Development of the Springbok rapid-prototyping system for board-level designs, as well as partitioning, pin assignment, and routing topology work for general multi-FPGA systems.
Triptych/Montage FPGA Architectures
Development of the Triptych and Montage FPGA architectures, architectures with improved densities over current commercial FPGAs.
Asynchronous Circuits
Survey of current asynchronous design methodologies, as well as the first FPGA for asynchronous circuits.
Logic Partitioning
Investigation into methods for efficiently breaking logic circuits into subcircuits, particularly for multi-FPGA implementations.

Selected Publications

(Surveys and introductory articles for a general audience)

Full list of publications

S. Hauck, A. DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

S. Hauck, "Asynchronous Design Methodologies: An Overview" (PDF), Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995.

S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998.

S. Hauck, "The Future of Reconfigurable Systems" (PDF), Keynote Address, 5th Canadian Conference on Field Programmable Devices, Montreal, June 1998.

S. Hauck, A. Agarwal, "Software Technologies for Reconfigurable Systems" (PDF), Northwestern University, Dept. of ECE Technical Report, 1996.

K. Compton, S. Hauck, "Reconfigurable Computing: A Survey of Systems and Software" (PDF), ACM Computing Surveys, Vol. 34, No. 2. pp. 171-210. June 2002.

S. Hauck, K. Compton, K. Eguro, M. Holland, S. Phillips, A. Sharma, "Totem: Domain-Specific Reconfigurable Logic", 2006.

M. Haselman, S. Hauck, "The Future of Integrated Circuits: A Survey of Nano-electronics", Proceedings of the IEEE, Vol. 98, No. 1, pp. 11-38, January 2010.

Current Graduate Students

Marshal Barrett (M.S. expected '13)
FPGAs in medical imaging.
Nathaniel McVicar (M.S. expected '11, Ph.D. expected '14)
Massively Parallel Processor Arrays.
Robin Panda (M.S. Winter '07, Ph.D. expected '12)
Implementation of Power-Efficient Coarse-Grained Reconfigurable Arrays.
Aaron Wood (Ph.D. expected '12)
Optimization of Massively Parallel Processor Arrays.

Former Graduate Students

Morgan Enos, M.S., "Replication for Logic Partitioning", September 1996. Consultant.
Oliver Stone, M.S., "A Comparison of ASIC Implementation Alternatives", October 1996. Joined Digital Equipment Corp.
Matt Hosler, M.S., "High-Performance Carry Chains for FPGAs", October 1997. Joined Motorola, then Arrow Electronics.
Guangyu Gu, M.S., "Accelerating Photoshop Applications with Reconfigurable Hardware", May 1999. Joined United Airlines, then Microsoft.
Venkatesh Karnam, M.S., "Applications of Reconfigurable Logic", March 2000. Joined Yahoo.
Thomas Fry, M.S., "Hyperspectral Image Compression on Reconfigurable Platforms", June 2001. Joined IBM, then went for MBA.
Melany Richmond, M.S., "A Lemple-Ziv based Configuration Management Architecture for Reconfigurable Computing", July 2001. Joined Quicksilver, then Zilog, then Cypress.
Chandra Mulpuri, M.S., "Runtime and Quality Tradeoffs in FPGA Placement and Routing", July 2001. Joined NEC, then Velogix, then Xilinx.
Zhiyuan Li, Ph.D., "Configuration Management for Reconfigurable Systems", November 2001. Joined Motorola.
Katherine Compton, M.S., "Programming Architectures for Run-Time Reconfigurable Systems", Fall 1999. Ph.D. "Architecture Generation of Customized Reconfigurable Hardware", September 2003. Faculty at University of Wisconsin - Madison.
Todd Owen, M.S. "FPGA Implementation of Error Correction and Improved SPIHT Compression for NASA Hyperspectral Images", June 2003. Joined Intel.
Kimberly Motonaga, M.S. "Encryption RaPiD: A Comparison of Custom and Standard-Cell Designs", December 2003. Joined Boeing.
Brigette Huang, M.S. 2D FPGA Layout, 2004. Joined Microsoft.
Mark Chang, M.S., "Adaptive Computing in NASA Multi-Spectral Image Processing", 1999. Ph.D., "Variable Precision Analysis for FPGA Synthesis", 2004. Faculty at Olin College.
Shawn Phillips, M.S. "Automatic Layout of Domain Specific Reconfigurable Subsystems for System-on-a-Chip", 2001. Ph.D. "Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip", 2004. Joined Annapolis Microsystems, then Johns Hopkins University - Applied Physics Lab.
Akshay Sharma, M.S. "Development of a Place and Route Tool for the RaPiD Architecture". Ph.D. "Place and Route Techniques for FPGA Architecture Advancement", 2005. Joined Actel, then Lecturer at the University of Washington, then Sun/Oracle.
Mark Holland, M.S. "Harnessing FPGAs for Computer Architecture Education, 2002. Ph.D. Automatic Creation of Product-Term-Based Reconfigurable Architectures for System-on-a-Chip, June 2005. Joined Annapolis Microsystems.
Mike Beauchamp, M.S. "Architectural Modifications to Enhance the Floating-Point Performance of FPGAs", August 2006. Joined MIPS.
Peter Grossman, M.S. "Architecture-Adaptive FPGA Placment", December 2006. Joined MIT Lincoln Labs.
Don DeWitt, M.S. "An FPGA Implementation of Statistical Based Positioning for Positron Emission Tomography", June 2008. Contractor with U.W. Dept. of Radiology.
Allan Carroll, M.S. "Characterizing the Quality of QuickRoute, A Heuristic Pipeline Router", Summer 2008. Joined FamilyLink.com.
Ken Eguro, M.S. "Encryption-Specific FPGA Architectures", Fall 2002. Ph.D. "Supporting High-Performance Pipelined Computation in Commodity-Style FPGAs", November 2008. Joined Microsoft Research.
Nikhil Subramanian, M.S. "A C-to-FPGA Solution for Accelerating Tomographic Reconstruction", Spring 2009. Joined Microsoft.
Nathan Johnson-Williams, M.S. "Design of a Real Time FPGA-based Three Dimensional Positioning Algorithm", Fall 2009. Joined Sandia National Labs, then Aerospace Corp.
Ziyuan Zhang, M.S. Winter 2010. Joined Bonneville Power Administration.
Jimmy Xu, M.S. Winter 2010. Joined Apple.
Ben Ylvisaker, Ph.D. Autumn 2011. Joined Grammatech Inc.
Brian Van Essen, Ph.D. Autumn 2011. Joined Lawrence Livermore National Labs.
Adam Knight, M.S. "Multi-Kernel Macah Support and Applications", Autumn 2011. Joined Intel.
Abhishek Raja, M.S. Autumn 2011. Joined AMD.
Mike Haselman, M.S. "Bitwidth Analysis of Floating-Point Computations for FPGA Implementations", Spring 2005. Ph.D. "FPGA-Based Pulse Processing for Positron Emission Tomography", Spring 2011. Joined Sandia National Labs.
Corey Olson, M.S. "An FPGA Acceleration of Short Read Human Genome Mapping", Spring 2011. Joined Pico Computing.
Maria Kim, M.S. "Accelerating Next Generation Genome Reassembly in FPGAs: Alignment Using Dynamic Programming Algorithms", Spring 2011.
Stephen Friedman, Ph.D. "Resource Sharing in Modulo-Scheduled Reconfigurable Architectures", Summer 2011. Joined Pixar.
James Pasko, M.S. Winter 2011. Joined Google.
Andrew Price, M.S. "Hephaestus: Solving the Heterogeneous, Highly Constrained Analog Placement Problem", Winter 2012. Joined Cypress.

Note: good information for all grad students can be found at:

Editorships

Associate Editor, International Journal of Reconfigurable Computing (IJRC), 2007 - present.

Guest Editor (with Toomas Plaks and others), ACM Transactions on Embedded Computing Systems, special issue on Configurable Computing: Configuring Algorithms, Processes, and Architecture, 2008.

Guest Editor (with Miriam Leeser and Russ Tessier), EURASIP Journal of Embedded Systems, special issue on Field-Programmable Gate Arrays in Embedded Systems, 2006.

Associate Editor, IEEE Transactions on VLSI Systems, 1999-2000.

Classes

Autumn 2011 - EE 471: Computer Design and Organization
Autumn 2011 - EE 541: Automated Layout of Integrated Circuits
Winter 2012 - EE 271: Digital Circuits and Systems

People