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Scott Hauck

Scott Hauck
Associate Professor
VLSI and Digital Systems
307Q EE/CSE
Box 352500
University of Washington
Seattle, WA 98195

Phone: (206) 221-5119
E-mail: hauck@ee.washington.edu

University of Washington, CSE, 1995 Ph.D., 1992 MS
University of California-Berkeley, EECS, 1990 B.S.

[Biosketch] [Honors] [Research Interests] [Selected Publications] [Patents] [Active Grants] [Current Grad Students] [Editorships] [Teaching]

Biosketch

He is an Associate Professor at the University of Washington's Department of Electrical Engineering, in the Digital Systems group, and an Adjunct in the Department of Computer Science and Engineering. His work is focused around FPGAs, chips that can be programmed and reprogrammed to implement complex digital logic. His interests are the application of FPGA technology to situations that can make use of their novel features: high-performance computing, reconfigurable subsystems for system-on-a-chip, computer architecture education, hyperspectral image compression, and other areas. His work encompasses VLSI, CAD, and applications of these devices.

He is editor (with Andre' DeHon) of a book on reconfigurable computing:
Scott Hauck, Andre' DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

Before returning to the University of Washington in 1999, he was an Assistant Professor at Northwestern University's Department of Electrical and Computer Engineering in the Computer Engineering group for four years.

He is the director of the Adaptive Computing Machines and Emulators Lab.

Honors

Finalist, U.W. Distinguished Teaching Award, 2008
Best Paper Award, Microelectronic Systems Education Conference, 2007.
Elixent, Inc. S.O.A.P.-Star: Spot On Award Program (employee achievement award), 2006.
Alfred P. Sloan Research Fellow (2001)
U.W. EE Department's Outstanding Research Advisor Award 2001
Senior Member, IEEE (2001)
June and Donald Brewer Junior Professorship, (Northwestern chair, given up in move to U.W.) 1999-2001
NSF CAREER award (1999)
1999 IEEE Circuits and Systems Society Transactions on VLSI Systems Best Paper Award
Northwestern University, ECE Department's Best Teacher of 1998/99
AT&T Bell Laboratories Graduate Fellowship
National Merit Finalist
Nominated, U.W. Distinguished Teaching Award, 2004, 2007, 2008
Nominated, U.W. College of Engineering Outstanding Faculty Member, 2004
Nominated, U.W. EE Department's Faculty Service Award, 2004
Nominated, U.W. EE Department's Outstanding Research Advisor Award 2003, 2004
Nominated, U.W. EE Department's Teaching Award 2001, 2003

Honors to students/advisees

Yang Research Award to Akshay Sharma (2005)
National Science Foundation Fellowship Honorable Mention to Michael Beauchamp (2003 & 2004)
Mary Gates Endowment for Students research training grant to Henry Lee (2003)
Intel Fellowship to Mark Chang (2002)
Lincoln Labs Fellowship to Shawn Phillips (2002)
Cabell Thesis Year Fellowship to Katherine Compton (2002)
U.W. EE Department's Outstanding Research Assistant Award to Mark Chang (2001-2002)
National Science Foundation Fellowships to Katherine Compton (1998), Mark Holland (2001)
1999 Motorola UPR Best Paper Award (to student Katherine Compton)

Research Interests

Reconfigurable Subsystems for System-on-a-Chip; FPGA Architectures, CAD tools, Compilers, and Applications; VLSI Design & CAD.

Research Projects

Heavily Pipelined Commodity FPGAs
Development of FPGA architectures and CAD tools that support mass-market commodity applications, yet still can provide huge performance increases for latency-tolerant designs.
FPGA-Based Medical Imaging in the MiCES System
Development of a high-performance PET scanner for animals and humans. Uses a large system of FPGAs to help detect photons emitted from radioactive materials injected into a host organism.
Totem: Reconfigurable Subsystems for System-on-a-Chip
Development of domain-specific and domain-adaptive FPGA architectures, layout generation, and physical design tools for adding reconfigurable subsystems into future complex ASIC designs.
CAD for FPGAs
Development of architecture-adaptive CAD tools for FPGAs, including the architecture-adaptive placer Independence, and the pipelining-aware router PipeRoute.
FPGA Support for Floating Point Computations
Development of FPGA architectures, libraries, CAD tools, and methodologies to efficiently support floating-point computations.
FPGA Logarithmic Number System Library
A library of basic units for logarithmic number systems, as well as format conversions.

Previous Research Efforts

FPGA-based Hyperspectral Image Compression
A NASA-sponsored investigation into spaceborne use of FPGAs. We are developing image compression algorithms to radically reduce the bandwidth requirements for downlinking NASA hyperspectral (multiple image bands, such as IR, UV, visible light) images.
FPGA Configuration Management
Exploration of methods to radically reduce the reconfiguration overhead in FPGA devices to enable efficient run-time-reconfiguration. We are also working on an configuration architecture layout to integrate these techniques into a complete chip design.
ALICE - ACME Labs Instant Computer
Development of an FPGA-based infrastructure and curriculum for computer architecture education.
Fast CAD
Development of fast placement & routing tools for logic emulation systems.
Variable Precision Analysis
Techniques to automatically optimize the bitwidths of MATLAB specifications of future FPGA hardware designs.
The Chimaera Reconfigurable Functional Unit
Development of a reconfigurable coprocessor for general purpose computing, as well as software mapping tools to support these systems.
Adaptive Computing
A DARPA-sponsored investigation into architectures, compilers, and configuration management for mass-market adaptive computing.
The MATCH Project (MATLAB Compilation for Heterogenous Systems)
Development of an automatic compiler for MATLAB programs targetted to a heterogenous system of FPGAs, DSPs, and microprocessor.
Hybrid FPGA/DSP Architectures
Exploring the use of FPGAs for digital signal processing, including the design of new architectures and cell structures.
Field-Programmable Systems-on-a-Chip
A DARPA-sponsored effort investigating architectures for hybrid FPGA, CPU, and DSP systems on a single chip. This research is aided by NASA Goddard through applications that exploit heterogenous systems.
Distributed High-Performance Computing for VLSI/CAD
The use of high-performance ATM Network of Workstations for VLSI/CAD applications.
Multi-FPGA Systems & Rapid-Prototyping
Development of the Springbok rapid-prototyping system for board-level designs, as well as partitioning, pin assignment, and routing topology work for general multi-FPGA systems.
Triptych/Montage FPGA Architectures
Development of the Triptych and Montage FPGA architectures, architectures with improved densities over current commercial FPGAs.
Asynchronous Circuits
Survey of current asynchronous design methodologies, as well as the first FPGA for asynchronous circuits.
Logic Partitioning
Investigation into methods for efficiently breaking logic circuits into subcircuits, particularly for multi-FPGA implementations.

Selected Publications

(Surveys and introductory articles for a general audience)

Full list of publications

S. Hauck, A. DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

S. Hauck, "Asynchronous Design Methodologies: An Overview" (PDF), Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995.

S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998.

S. Hauck, "The Future of Reconfigurable Systems" (PDF), Keynote Address, 5th Canadian Conference on Field Programmable Devices, Montreal, June 1998.

S. Hauck, A. Agarwal, "Software Technologies for Reconfigurable Systems" (PDF), Northwestern University, Dept. of ECE Technical Report, 1996.

K. Compton, S. Hauck, "Reconfigurable Computing: A Survey of Systems and Software" (PDF), ACM Computing Surveys, Vol. 34, No. 2. pp. 171-210. June 2002.

S. Hauck, K. Compton, K. Eguro, M. Holland, S. Phillips, A. Sharma, "Totem: Domain-Specific Reconfigurable Logic", 2006.

M. Haselman, S. Hauck, "The Future of Integrated Circuits: A Survey of Nano-electronics", submitted to Proceedings of the IEEE.

Active Grants

National Science Foundation, 11/04-10/08. Scott Hauck, Achieving High-Performance Reconfigurable Computing in Commodity Devices.

National Institutes of Health, 2006-2011. Thomas K. Lewellen, Robert S. Miyaoka, Paul E. Kinahan, Marie Janes, Scott A. Hauck, High Resolution Detectors for Oncology Applications.

Department of Energy, 9/07 - 8/10. Carl Ebeling, Scott Hauck, A High-Performance, Low-Power Configurable Fabric for Embedded Applications.

Zecotek Medical Systems, 3/06 - 2/11. Thomas K. Lewellen, Robert S. Miyaoka, Paul E. Kinahan, Scott A. Hauck, Marie Janes, High Resolution Positron Emission Tomograph Detector and Electronics Development.

Current Graduate Students

Allan Carroll (Ph.D. expected '11)
CAD for Coarse-Grained Reconfigurable Arrays.
Don DeWitt (M.S. expected Spring '08)
High-Performance PET imaging with FPGAs.
Ken Eguro (M.S. Fall '02, Ph.D. expected '08)
High-performance Pipelining on Commercial FPGAs.
Stephen Friedman (Ph.D. expected '09)
Optimization of Coarse-Grained Reconfigurable Arrays.
Mike Haselman (M.S. Spring '05, Ph.D. expected '08)
High-Performance PET imaging with FPGAs.
Anindita Mitra (M.S. expected '09)
Hardware Design with Coarse-Grained Reconfigurable Arrays.
Robin Panda (M.S. Winter '07, Ph.D. expected '10)
Implementation of Power-Efficient Coarse-Grained Reconfigurable Arrays.
Nikhil Subramanian (M.S. expected '09)
Image Compression on Coarse-Grained Reconfigurable Arrays.
Brian Van Essen (Ph.D. expected '09)
Architectures for Power-Efficient Coarse-Grained Reconfigurable Arrays.
Aaron Wood (Ph.D. expected '10)
Implementation of Power-Efficient Coarse-Grained Reconfigurable Arrays.
Benjamin Ylvisaker (Ph.D. expected '09)
Languages for Reconfigurable Coprocessors.

Former Graduate Students

Morgan Enos, M.S., "Replication for Logic Partitioning", September 1996.
Oliver Stone, M.S., "A Comparison of ASIC Implementation Alternatives", October 1996.
Matt Hosler, M.S., "High-Performance Carry Chains for FPGAs", October 1997.
Guangyu Gu, M.S., "Accelerating Photoshop Applications with Reconfigurable Hardware", May 1999.
Venkatesh Karnam, M.S., "Applications of Reconfigurable Logic", March 2000.
Thomas Fry, M.S., "Hyperspectral Image Compression on Reconfigurable Platforms", June 2001.
Melany Richmond, M.S., "A Lemple-Ziv based Configuration Management Architecture for Reconfigurable Computing", July 2001.
Chandra Mulpuri, M.S., "Runtime and Quality Tradeoffs in FPGA Placement and Routing", July 2001.
Zhiyuan Li, Ph.D., "Configuration Management for Reconfigurable Systems", November 2001.
Katherine Compton, M.S., "Programming Architectures for Run-Time Reconfigurable Systems", Fall 1999. Ph.D. "Architecture Generation of Customized Reconfigurable Hardware", September 2003.
Todd Owen, M.S. "FPGA Implementation of Error Correction and Improved SPIHT Compression for NASA Hyperspectral Images", June 2003.
Kimberly Motonaga, M.S. "Encryption RaPiD: A Comparison of Custom and Standard-Cell Designs", December 2003.
Brigette Huang, M.S. 2D FPGA Layout, 2004.
Mark Chang, M.S., "Adaptive Computing in NASA Multi-Spectral Image Processing", 1999. Ph.D., "Variable Precision Analysis for FPGA Synthesis", 2004.
Shawn Phillips, M.S. "Automatic Layout of Domain Specific Reconfigurable Subsystems for System-on-a-Chip", 2001. Ph.D. "Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip", 2004.
Akshay Sharma, M.S. "Development of a Place and Route Tool for the RaPiD Architecture". Ph.D. "Place and Route Techniques for FPGA Architecture Advancement", 2005.
Mark Holland, M.S. "Harnessing FPGAs for Computer Architecture Education, 2002. Ph.D. Automatic Creation of Product-Term-Based Reconfigurable Architectures for System-on-a-Chip, June 2005.
Mike Beauchamp, M.S. "Architectural Modifications to Enhance the Floating-Point Performance of FPGAs", August 2006.
Peter Grossman, M.S. "Architecture-Adaptive FPGA Placment", December 2006.

Note: good information for all grad students can be found at:

Editorships

Associate Editor, International Journal of Reconfigurable Computing (IJRC), 2007 - present.

Guest Editor (with Miriam Leeser and Russ Tessier), EURASIP Journal of Embedded Systems, special issue on Field-Programmable Gate Arrays in Embedded Systems, 2006.

Associate Editor, IEEE Transactions on VLSI Systems, 1999-2000.

Classes

Autumn 2007 - EE 271: Digital Circuits and Systems
Winter 2008 - EE 541: Automated Layout of Integrated Circuits
Winter 2008 - EE 471: Computer Design and Organization