The last 15 years has witnessed revolutionary changes in mobile computing and wireless communication. This was fueled in large part through Moore’s Law, coupled with research and development of new highly-integrated, silicon CMOS devices which transformed large bulky transceiver components into a single chip for wireless applications. These single-chip radios freed up valuable space for more memory and powerful processors, making the modern smartphone, as we know it today, so common and ubiquitous. Although the architectures, circuits, and system-level design methodologies to realize these low-cost, highly-integrated RF ICs have largely been defined, questions remain on how to enable chips for emerging applications in an era of large scale data acquisition, and communication, for a variety of devices ranging in use from wireless sensing, to high-speed mobile and point-to-point data communication. Recent work at the University of Washington’s FAST lab, has explored some of these challenges, and developed all-CMOS chips which demonstrate concepts to address some of the future IC challenges associated with ultra-broadband communication. This presentation begins with a description of a 50-70 GHz broadband receiver intended for use in a high-element phased-array system. This receiver utilizes a low-power heterodyne architecture to reduce LO power consumption, while passing the entire 20 GHz bandwidth through the IF, to baseband. The IF stage has one of the highest fractional bandwidths reported to date. Other broadband techniques are described with a compact 24-54 GHz bandpass distributed amplifier which recursively exploits Norton Transforms to reduce silicon area while improving selectivity, and maintaining a high fractional bandwidth. Other methods to enhance wireless bandwidth by exploiting underutilized duplex bands in FDD systems are explored. A description of a passive, and noiseless 40nm CMOS TX-to-RX cancellation technique is described which reduces self-interference of a WCDMA frontend. Other loosely related projects which exploit the nanometer dimensions of modern silicon processes include a new PA/transmitter approach intended for use in long-range sensor communication. In addition, a novel silicon approach for readout electronics in a highly dense PET imaging detector array will be discussed. This project, in conjunction with the University of Washington Radiology Department, has recently fabricated a 130nm CMOS chip which includes a 64-channel readout array with a novel approach for threshold detection. The talk will conclude with some thoughts on a high-voltage compliant neural stimulation systems realized in conventional low-voltage CMOS technologies. This work, which is currently in progress through the Center for Sensorimotor Neural Engineering (CSNE), and seeks to realize an implantable system suitable for ECoG surface stimulation.
Jacques “Chris”tophe Rudell received degrees in electrical engineering from the University of Michigan (BS), and UC Berkeley (MS, PhD). After completing his degrees, he worked for several years as an RF IC designer at Berkana Wireless (now Qualcomm), and Intel Corporation. In January 2009, he joined the faculty at the University of Washington, Seattle, as an Assistant Professor of Electrical Engineering. While a PhD student at UC Berkeley, Dr. Rudell received the Demetri Angelakos Memorial Achievement Award, a citation given to one student per year by the EECS department. He has twice been co-recipient of the best paper awards at the International Solid-State Circuits Conference, the first of which was the 1998 Jack Kilby Award, followed by the 2001 Lewis Winner Award. He received the 2008 ISSCC best evening session award, and the 2011 RFIC Symposium best student paper award. Dr. Rudell served on the ISSCC technical program committee (2003-2010), and on the MTT-IMS Radio Frequency Integrated Circuits (RFIC) Symposium steering committee (2002-2013), where he was the 2013 General Chair. He is also an Associate Editor for the Journal of Solid-State Circuits (2009-present).