Abstract
The minimum feature size of CMOS technology will reach 10nm in ten years. Beyond the 10nm node, several emerging technologies have been actively researched as alternatives, including nano-tubes and molecular devices. Such aggressive scaling inevitably leads to vastly increased power dissipation, process variations and reliability degradation, posing major challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. This new paradigm requires Predictive Technology Model (PTM) for future generations, including both nanoscale CMOS and post-silicon devices. Such a capability of technological prediction is critical to identify emergent challenges and adaptively make design decisions up front.
In this context, this talk will present new predictive modeling efforts that envision nanoscale technology advances and address key design needs. Particular topics include: the foundation of predictive modeling, PTM for both traditional CMOS and alternative structures, such as FinFET, and PTM for carbon nano-tubes. These newly developed models enable early stage design exploration with increasing technology diversity. This talk will end with a discussion on future heterogeneous system integration, helping shed light on design opportunities and challenges in the nanoelectronics era. PTM is available at http://www.eas.asu.edu/~ptm.
Biography
Dr. Yu (Kevin) Cao received the B.S. degree in physics from Peking University in 1996. He received the M.A. degree in biophysics and the Ph.D. degree in electrical engineering from University of California, Berkeley, in 1999 and 2002, respectively. After working as a post-doctoral researcher at the Berkeley Wireless Research Center (BWRC), he joined Arizona State University in 2004 where he is now Assistant Professor of Electrical Engineering. He has published more than 70 articles and coauthored one book on nano-CMOS physical and circuit design. His research interests include physical modeling of nanoscale technologies, design solutions for variability and reliability, and reliable integration of post-silicon technologies.
Dr. Cao received the 2007 Best Paper Award at ISLPED, the 2006 NSF CAREER Award, the 2006 and 2007 IBM Faculty Award, the 2004 Best Paper Award at ISQED, and the 2000 Beatrice Winner Award at ISSCC. He has served on the technical program committee of many conferences and is a member of the IEEE EDS Compact Modeling Technical Committee.
